| Summary: | Regression: DP outputs out of sync on dual-DP tiled 5k screen | ||||||||||
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| Product: | DRI | Reporter: | Tomas Bzatek <bugs> | ||||||||
| Component: | DRM/AMDgpu | Assignee: | Default DRI bug account <dri-devel> | ||||||||
| Status: | RESOLVED MOVED | QA Contact: | |||||||||
| Severity: | normal | ||||||||||
| Priority: | medium | CC: | bugs, harry.wentland, nicholas.kazlauskas, sunpeng.li, utenkov.vv87 | ||||||||
| Version: | DRI git | ||||||||||
| Hardware: | x86-64 (AMD64) | ||||||||||
| OS: | Linux (All) | ||||||||||
| See Also: |
https://bugs.freedesktop.org/show_bug.cgi?id=105651 https://bugs.freedesktop.org/show_bug.cgi?id=101633 |
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| Whiteboard: | |||||||||||
| i915 platform: | i915 features: | ||||||||||
| Attachments: |
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Description
Tomas Bzatek
2019-05-13 11:04:19 UTC
Please attach the corresponding output of dmesg and Xorg log file. Created attachment 144250 [details]
dmesg drm.debug=0x1e (kernel 5.1.0-rc5-g9d6fea5744d6)
This is drm-next-5.2 branch, head 9d6fea5744d6798353f
"drm/amdgpu/psp: move psp version specific function pointers to early_init"
Created attachment 144251 [details]
Xorg.0.log (kernel 5.1.0-rc5-g9d6fea5744d6)
Created attachment 144252 [details]
dmesg drm.debug=0x1e (kernel 4.20.0-zen-g742adf1bca12-dirty)
For the record, this is a custom 4.20.0 kernel that is proven realiable.
Basically agd5f drm-next-4.21 branch at 674e78acae0dfb4beb5613
"drm/amd/display: Add fast path for cursor plane updates"
Have same issue on Vega FE + Dell UP2715K. Also it may be related to this bug: https://bugs.freedesktop.org/show_bug.cgi?id=105651 Manual bisect so far: good 0f74e484912626 drm/amd/display: 3.2.15 bad cf7d98d254e9ff drm/amd/display: 3.2.16 The offending commit is commit 5fc0cbfad4564856ee0f323d3f88a7cff19cc3f1 Author: Wenjing Liu <Wenjing.Liu@amd.com> Date: Fri Jan 18 18:19:51 2019 -0500 drm/amd/display: determine if a pipe is synced by plane state Still no luck with 5.1.10 Broken in 5.3-rc1 Workaround to revert 5fc0cbfad4564856ee0f323d3f88a7cff19cc3f1 is still working. Just added some debug to rc3 and tried to check what happens(in context of 5fc0cbfad4564856ee0f323d3f88a7cff19cc3f1). So in program_timing_sync() there is preparing of groups of pipes for sync. And looks like(in my case) pipe_set[j]->plane_state is always true, and all elements > 0 is removed from the pipe_set in this case, hence group_size == 1 and dc->hwss.enable_timing_synchronization() newer called. Contrary with old check !pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg) is always false and we have our sync. Maybe it should be !pipe_set[j]->plane_state instead of pipe_set[j]->plane_state ? I applied this change to my 5.3.0-rc3 build and so far everything looks ok. I do not understand the purpose of is_blanked or plane_state, maybe with mst hubs or other stuff it may be a different story, but in my simple config it looks like just a typo. -- GitLab Migration Automatic Message -- This bug has been migrated to freedesktop.org's GitLab instance and has been closed from further activity. You can subscribe and participate further through the new bug through this link to our GitLab instance: https://gitlab.freedesktop.org/drm/amd/issues/781. |
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