Bug 111844

Summary: [CI][RESUME] igt@kms_psr@psr2-* fail - Failed assertion: psr_wait_entry_if_enabled(data)
Product: DRI Reporter: Lakshmi <lakshminarayana.vudum>
Component: DRM/IntelAssignee: Intel GFX Bugs mailing list <intel-gfx-bugs>
Status: CLOSED WONTFIX QA Contact: Intel GFX Bugs mailing list <intel-gfx-bugs>
Severity: not set    
Priority: not set CC: intel-gfx-bugs, jose.souza
Version: DRI git   
Hardware: Other   
OS: All   
Whiteboard:
i915 platform: TGL i915 features: display/PSR

Description Lakshmi 2019-09-27 13:51:52 UTC 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/re-tgl1-display/igt@kms_psr@psr2_cursor_mmap_cpu.html
Starting subtest: psr2_cursor_mmap_cpu
(kms_psr:1144) CRITICAL: Test assertion failure function test_setup, file ../tests/kms_psr.c:394:
(kms_psr:1144) CRITICAL: Failed assertion: psr_wait_entry_if_enabled(data)
Subtest psr2_cursor_mmap_cpu failed.
Comment 1 Lakshmi 2019-09-27 13:54:11 UTC 
(In reply to Lakshmi from comment #0)
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/re-tgl1-display/
> igt@kms_psr@psr2_cursor_mmap_cpu.html
> Starting subtest: psr2_cursor_mmap_cpu
> (kms_psr:1144) CRITICAL: Test assertion failure function test_setup, file
> ../tests/kms_psr.c:394:
> (kms_psr:1144) CRITICAL: Failed assertion: psr_wait_entry_if_enabled(data)
> Subtest psr2_cursor_mmap_cpu failed.

These are the failures from resume runs where I couldn't find the dmesg. So, I couldn't confirm if it's a duplicate of Bug 111743.
Comment 2 CI Bug Log 2019-09-27 13:54:41 UTC 
The CI Bug Log issue associated to this bug has been updated.

### New filters associated

* re-tgl1-display: igt@kms_psr@psr2-* fail - Failed assertion: psr_wait_entry_if_enabled(data)
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14335/re-tgl-u/igt@kms_psr@psr2_basic.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14335/re-tgl-u/igt@kms_psr@psr2_cursor_blt.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14335/re-tgl-u/igt@kms_psr@psr2_cursor_mmap_cpu.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14335/re-tgl-u/igt@kms_psr@psr2_cursor_mmap_gtt.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14335/re-tgl-u/igt@kms_psr@psr2_cursor_plane_move.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14335/re-tgl-u/igt@kms_psr@psr2_cursor_plane_onoff.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14335/re-tgl-u/igt@kms_psr@psr2_cursor_render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14335/re-tgl-u/igt@kms_psr@psr2_dpms.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14335/re-tgl-u/igt@kms_psr@psr2_no_drrs.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14335/re-tgl-u/igt@kms_psr@psr2_primary_blt.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14335/re-tgl-u/igt@kms_psr@psr2_primary_mmap_cpu.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14335/re-tgl-u/igt@kms_psr@psr2_primary_mmap_gtt.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14335/re-tgl-u/igt@kms_psr@psr2_primary_page_flip.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14335/re-tgl-u/igt@kms_psr@psr2_primary_render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14335/re-tgl-u/igt@kms_psr@psr2_sprite_blt.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14335/re-tgl-u/igt@kms_psr@psr2_sprite_mmap_cpu.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14335/re-tgl-u/igt@kms_psr@psr2_sprite_mmap_gtt.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14335/re-tgl-u/igt@kms_psr@psr2_sprite_plane_move.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14335/re-tgl-u/igt@kms_psr@psr2_sprite_plane_onoff.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14335/re-tgl-u/igt@kms_psr@psr2_sprite_render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14335/re-tgl-u/igt@kms_psr@psr2_suspend.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14450/re-tgl-u/igt@kms_psr@psr2_basic.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14450/re-tgl-u/igt@kms_psr@psr2_cursor_blt.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14450/re-tgl-u/igt@kms_psr@psr2_cursor_mmap_cpu.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14450/re-tgl-u/igt@kms_psr@psr2_cursor_mmap_gtt.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14450/re-tgl-u/igt@kms_psr@psr2_cursor_plane_move.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14450/re-tgl-u/igt@kms_psr@psr2_cursor_plane_onoff.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14450/re-tgl-u/igt@kms_psr@psr2_cursor_render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14450/re-tgl-u/igt@kms_psr@psr2_dpms.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14450/re-tgl-u/igt@kms_psr@psr2_no_drrs.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14450/re-tgl-u/igt@kms_psr@psr2_primary_blt.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14450/re-tgl-u/igt@kms_psr@psr2_primary_mmap_cpu.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14450/re-tgl-u/igt@kms_psr@psr2_primary_mmap_gtt.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14450/re-tgl-u/igt@kms_psr@psr2_primary_page_flip.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14450/re-tgl-u/igt@kms_psr@psr2_primary_render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14450/re-tgl-u/igt@kms_psr@psr2_sprite_blt.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14450/re-tgl-u/igt@kms_psr@psr2_sprite_mmap_cpu.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14450/re-tgl-u/igt@kms_psr@psr2_sprite_mmap_gtt.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14450/re-tgl-u/igt@kms_psr@psr2_sprite_plane_move.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14450/re-tgl-u/igt@kms_psr@psr2_sprite_plane_onoff.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14450/re-tgl-u/igt@kms_psr@psr2_sprite_render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14450/re-tgl-u/igt@kms_psr@psr2_suspend.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/re-tgl1-display/igt@kms_psr@psr2_basic.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/re-tgl1-display/igt@kms_psr@psr2_cursor_blt.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/re-tgl1-display/igt@kms_psr@psr2_cursor_mmap_cpu.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/re-tgl1-display/igt@kms_psr@psr2_cursor_mmap_gtt.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/re-tgl1-display/igt@kms_psr@psr2_cursor_plane_move.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/re-tgl1-display/igt@kms_psr@psr2_cursor_plane_onoff.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/re-tgl1-display/igt@kms_psr@psr2_cursor_render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/re-tgl1-display/igt@kms_psr@psr2_dpms.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/re-tgl1-display/igt@kms_psr@psr2_no_drrs.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/re-tgl1-display/igt@kms_psr@psr2_primary_blt.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/re-tgl1-display/igt@kms_psr@psr2_primary_mmap_cpu.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/re-tgl1-display/igt@kms_psr@psr2_primary_mmap_gtt.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/re-tgl1-display/igt@kms_psr@psr2_primary_page_flip.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/re-tgl1-display/igt@kms_psr@psr2_primary_render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/re-tgl1-display/igt@kms_psr@psr2_sprite_blt.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/re-tgl1-display/igt@kms_psr@psr2_sprite_mmap_cpu.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/re-tgl1-display/igt@kms_psr@psr2_sprite_mmap_gtt.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/re-tgl1-display/igt@kms_psr@psr2_sprite_plane_move.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/re-tgl1-display/igt@kms_psr@psr2_sprite_plane_onoff.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/re-tgl1-display/igt@kms_psr@psr2_sprite_render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/re-tgl1-display/igt@kms_psr@psr2_suspend.html
Comment 3 CI Bug Log 2019-09-27 13:54:57 UTC 
A CI Bug Log filter associated to this bug has been updated:

{- re-tgl1-display: igt@kms_psr@psr2-* fail - Failed assertion: psr_wait_entry_if_enabled(data) -}
{+ re-tgl1-display: igt@kms_psr@psr2-* fail - Failed assertion: psr_wait_entry_if_enabled(data) +}


  No new failures caught with the new filter
Comment 4 Jose Roberto de Souza 2019-09-27 17:08:29 UTC 
re-tgl1-display is using one of the AUO panels that have issues with PSR2, within 100ms of PSR2 enable, panel already have a RFB and VSC uncorrectable errors.

<7>[   11.186540] [drm:drm_dp_read_desc] DP sink: OUI 00-1c-f8 dev-ID \223\006UA\023\001 HW-rev 10.0 SW-rev 2.24 quirks 0x0000

<7>[   11.347289] [drm:intel_psr_enable_locked [i915]] Enabling PSR2

<7>[   11.463660] [drm:intel_psr_short_pulse [i915]] PSR sink internal error, disabling PSR
<7>[   11.463722] [drm:intel_psr_disable_locked [i915]] Disabling PSR2
<7>[   11.470971] [drm:intel_psr_short_pulse [i915]] PSR RFB storage error, disabling PSR
<7>[   11.471021] [drm:intel_psr_short_pulse [i915]] PSR VSC SDP uncorrectable error, disabling PSR
Comment 5 Vanshidhar Konda 2019-10-30 18:37:42 UTC 
It seems like the igt@kms_psr test has been disabled from running on TGL machines for now. This issue has not been hit in 1 month now. Closing for now, can be reopened if we hit the issue later.
Comment 6 Jani Saarinen 2019-10-30 19:29:17 UTC 
Not sure what you mean:
 http://gfx-ci.fi.intel.com/tree/drm-tip/index.html?testfilter=psr&hosts=tgl
Comment 8 Vanshidhar Konda 2019-10-30 20:43:17 UTC 
kms_psr tests have not been running or possibly skipping on the re-tgl1-display machine for a while now:
http://gfx-ci.fi.intel.com/cibuglog-ng/results/knownfailures?query=test_name+ICONTAINS+%22kms_psr%22+AND+machine_name%3D%27re-tgl1-display%27
Comment 9 Jani Saarinen 2019-10-31 05:21:51 UTC 
That is true. That was just temporary system in CI. Not anymore there.

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