Bug 111743 - [CI][DRMTIP] igt@kms_psr@psr2_sprite_render - fail - Failed assertion: psr_wait_entry_if_enabled(data), PSR sink implementation is not reliable
Summary: [CI][DRMTIP] igt@kms_psr@psr2_sprite_render - fail - Failed assertion: psr_wa...
Status: RESOLVED WORKSFORME
Alias: None
Product: DRI
Classification: Unclassified
Component: DRM/Intel (show other bugs)
Version: DRI git
Hardware: Other All
: not set not set
Assignee: Intel GFX Bugs mailing list
QA Contact: Intel GFX Bugs mailing list
URL:
Whiteboard:
Keywords:
Depends on:
Blocks:
 
Reported: 2019-09-19 09:21 UTC by Lakshmi
Modified: 2019-10-07 06:01 UTC (History)
2 users (show)

See Also:
i915 platform: TGL
i915 features: display/PSR

Attachments

Description Lakshmi 2019-09-19 09:21:09 UTC 
https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_371/fi-tgl-u2/igt@kms_psr@psr2_sprite_render.html

Starting subtest: psr2_sprite_render
(kms_psr:1274) CRITICAL: Test assertion failure function test_setup, file ../tests/kms_psr.c:394:
(kms_psr:1274) CRITICAL: Failed assertion: psr_wait_entry_if_enabled(data)
Subtest psr2_sprite_render failed.
Comment 1 CI Bug Log 2019-09-19 09:22:53 UTC 
The CI Bug Log issue associated to this bug has been updated.

### New filters associated

* fi-tgl-u2 - igt@kms_psr@psr2_sprite_render - fail - Failed assertion: psr_wait_entry_if_enabled(data), PSR sink implementation is not reliable
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_371/fi-tgl-u2/igt@kms_psr@psr2_sprite_render.html
Comment 2 Jose Roberto de Souza 2019-09-19 17:11:05 UTC 
A FIFO underrun caused a PSR CRC mismatch and after that we don't enable PSR anymore to avoid further glitches.

<3>[  135.106379] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe A FIFO underrun
<7>[  135.106573] [drm:intel_fbc_underrun_work_fn [i915]] Disabling FBC due to FIFO underrun.
<7>[  135.122201] [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x00010000, dig 0x00000889, pins 0x00000010, long 0x00000000
<7>[  135.122247] [drm:intel_hpd_irq_handler [i915]] digital hpd on [ENCODER:275:DDI A] - short
<7>[  135.122318] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on [ENCODER:275:DDI A] - short
<7>[  135.123563] [drm:intel_dp_read_dpcd [i915]] Base DPCD: 14 0a 82 41 00 00 01 c0 02 00 00 00 0f 09 80
<7>[  135.123601] [drm:intel_dp_read_dpcd [i915]] DPCD: 14 0a 82 c1 00 00 01 c0 02 00 00 00 0f 09 80
<7>[  135.124530] [drm:intel_psr_enable_locked [i915]] Enabling PSR1
<7>[  135.125051] [drm:intel_ddi_update_pipe [i915]] Panel doesn't support DRRS
<3>[  135.126007] [drm:intel_psr_short_pulse [i915]] *ERROR* PSR Link CRC error, disabling PSR

We probably have issues open for the TGL FIFO underrruns, fixing those would fix this one.
Comment 3 Jani Saarinen 2019-10-07 06:01:17 UTC 
This has now been passing lately on shards and fi-tgl-u. On one (re-tgl1-display) panel need to be checked.

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