| Summary: | [SNB/IVB/HSW VT-d] Align scanouts to 256KiB | ||||||
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| Product: | DRI | Reporter: | Chris Wilson <chris> | ||||
| Component: | DRM/Intel | Assignee: | Intel GFX Bugs mailing list <intel-gfx-bugs> | ||||
| Status: | CLOSED FIXED | QA Contact: | Intel GFX Bugs mailing list <intel-gfx-bugs> | ||||
| Severity: | normal | ||||||
| Priority: | medium | ||||||
| Version: | XOrg git | ||||||
| Hardware: | Other | ||||||
| OS: | All | ||||||
| Whiteboard: | |||||||
| i915 platform: | i915 features: | ||||||
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Description
Chris Wilson
2013-01-20 15:38:59 UTC
s/128 pages/128 PTEs/ The pages are not accessed, only the PTEs, so we just need to enlarge the scanout space. Created attachment 75174 [details] [review] Align scanouts to 256KiB Thinking about the padding, I think we don't need it whilst we always populate the unused PTE with the shadow page. commit e4054a376b6c357c68215a4e2db2636a8a05e7ba Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Tue Mar 5 14:52:39 2013 +0000 drm/i915: Apply alignment restrictions on scanout surfaces for VT-d |
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