Bug 59626 - [SNB/IVB/HSW VT-d] Align scanouts to 256KiB
Summary: [SNB/IVB/HSW VT-d] Align scanouts to 256KiB
Status: CLOSED FIXED
Alias: None
Product: DRI
Classification: Unclassified
Component: DRM/Intel (show other bugs)
Version: XOrg git
Hardware: Other All
: medium normal
Assignee: Intel GFX Bugs mailing list
QA Contact: Intel GFX Bugs mailing list
URL:
Whiteboard:
Keywords:
Depends on:
Blocks:
 
Reported: 2013-01-20 15:38 UTC by Chris Wilson
Modified: 2017-07-24 22:59 UTC (History)
0 users

See Also:
i915 platform:
i915 features:

Attachments
Align scanouts to 256KiB (1.56 KB, patch)
2013-02-20 14:45 UTC, Chris Wilson 		no flags Details | Splinter Review
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Description Chris Wilson 2013-01-20 15:38:59 UTC 
'To prevent false VT-d type 6 error, the scanouts must be 256KiB aligned, and require an extra 128 pages of padding afterward'
Comment 1 Chris Wilson 2013-01-20 15:41:07 UTC 
s/128 pages/128 PTEs/ The pages are not accessed, only the PTEs, so we just need to enlarge the scanout space.
Comment 2 Chris Wilson 2013-02-20 14:45:20 UTC 
Created attachment 75174 [details] [review]
Align scanouts to 256KiB
Comment 3 Chris Wilson 2013-03-05 14:10:45 UTC 
Thinking about the padding, I think we don't need it whilst we always populate the unused PTE with the shadow page.
Comment 4 Chris Wilson 2013-03-27 10:11:49 UTC 
commit e4054a376b6c357c68215a4e2db2636a8a05e7ba
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Tue Mar 5 14:52:39 2013 +0000

    drm/i915: Apply alignment restrictions on scanout surfaces for VT-d

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