Summary: | [BDW Bisected]Piglit spec_EXT_framebuffer_multisample_formats_2 is core dumped | ||
---|---|---|---|
Product: | Mesa | Reporter: | lu hua <huax.lu> |
Component: | Drivers/DRI/i965 | Assignee: | Ian Romanick <idr> |
Status: | VERIFIED DUPLICATE | QA Contact: | Intel 3D Bugs Mailing List <intel-3d-bugs> |
Severity: | normal | ||
Priority: | high | ||
Version: | unspecified | ||
Hardware: | All | ||
OS: | Linux (All) | ||
Whiteboard: | |||
i915 platform: | i915 features: |
Description
lu hua
2014-08-26 06:01:28 UTC
Bisect shows: 2f28a0dc23165123cf1e8b5942acad37878edd8a is the first bad commit commit 2f28a0dc23165123cf1e8b5942acad37878edd8a Author: Kristian Høgsberg <krh@bitplanet.net> AuthorDate: Mon Jul 7 16:44:58 2014 -0700 Commit: Kristian Høgsberg <krh@bitplanet.net> CommitDate: Fri Aug 15 11:25:47 2014 -0700 i965: Implement fast color clears using meta operations This patch uses the infrastructure put in place by previous patches to implement fast color clears and replicated color clears in terms of meta operations. This works all the way back to gen7 where fast clear was introduced and adds support for fast clear on gen8. It replaces the blorp path completely and improves on a few cases. Layered clears are now done using instanced rendering and multiple render-target clears use a MRT shader with rep16 writes. Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> Acked-by: Kenneth Graunke <kenneth@whitecape.org> *** This bug has been marked as a duplicate of bug 83081 *** |
Use of freedesktop.org services, including Bugzilla, is subject to our Code of Conduct. How we collect and use information is described in our Privacy Policy.