Bug 83506

Summary:	[UBO] row_major layout ignored inside structures
Product:	Mesa	Reporter:	Ian Romanick <idr>
Component:	glsl-compiler	Assignee:	Ian Romanick <idr>
Status:	RESOLVED FIXED	QA Contact:	Intel 3D Bugs Mailing List <intel-3d-bugs>
Severity:	normal
Priority:	medium
Version:	git
Hardware:	Other
OS:	All
Whiteboard:
i915 platform:		i915 features:
Attachments:	Test case

Description Ian Romanick 2014-09-04 18:13:56 UTC

Created attachment 105762 [details]
Test case

The problem appears to be that the i965 backend generates the load of s[1].bv2.x from offset 80 even when m41_1 is row-major.  When m41_1 is row-major, s[1].bv2.x should be at offset 64.  This is correctly reported via the GL API.

The attached test reproduces the issue.

Comment 1 Ian Romanick 2014-09-05 15:29:25 UTC

Not the backend's problem.  The IR generated by the ubo_load lowering pass is incorrect.

  (swiz x (expression bvec2 ubo_load (constant uint (0)) (constant uint (80))))

Comment 2 Ian Romanick 2014-12-17 19:21:12 UTC

This test passes on master and 10.4.  It was fixed with all the UBO work I did earlier in the year, but I forgot to close the bug.

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