Created attachment 105762 [details]
The problem appears to be that the i965 backend generates the load of s.bv2.x from offset 80 even when m41_1 is row-major. When m41_1 is row-major, s.bv2.x should be at offset 64. This is correctly reported via the GL API.
The attached test reproduces the issue.
Not the backend's problem. The IR generated by the ubo_load lowering pass is incorrect.
(swiz x (expression bvec2 ubo_load (constant uint (0)) (constant uint (80))))
This test passes on master and 10.4. It was fixed with all the UBO work I did earlier in the year, but I forgot to close the bug.