| Summary: | Randon R7 240 doesn't work on 16KiB page size platform | ||
|---|---|---|---|
| Product: | Mesa | Reporter: | Heiher <r> |
| Component: | Drivers/Gallium/r600 | Assignee: | Default DRI bug account <dri-devel> |
| Status: | RESOLVED FIXED | QA Contact: | Default DRI bug account <dri-devel> |
| Severity: | normal | ||
| Priority: | medium | ||
| Version: | git | ||
| Hardware: | Other | ||
| OS: | Linux (All) | ||
| Whiteboard: | |||
| i915 platform: | i915 features: | ||
| Attachments: |
winsys/radeon: Use CPU page size instead of hardcoding 4096
winsys/radeon: Use CPU page size instead of hardcoding 4096 |
||
|
Description
Heiher
2015-10-30 16:12:04 UTC
GPU pages are 4k. These functions are dealing with the GPU's virtual address space, not the CPU's. What sort of problem are you seeing? Created attachment 119338 [details] [review] winsys/radeon: Use CPU page size instead of hardcoding 4096 Does this patch fix it? Created attachment 119339 [details] [review] winsys/radeon: Use CPU page size instead of hardcoding 4096 Updated patch which leaves the 4K alignment for the VM range start address. (In reply to Alex Deucher from comment #1) > GPU pages are 4k. These functions are dealing with the GPU's virtual > address space, not the CPU's. What sort of problem are you seeing? dmesg outputs when X server starting: [ 1071.083005] radeon 0000:02:00.0: bo 98000001e5d76000 va 0x0000000802 conflict with (bo 98000001e5d76800 0x0000000800 0x0000000803) [ 1071.095425] radeon 0000:02:00.0: bo 98000001e5d76000 va 0x0000000802 conflict with (bo 98000001e5d76800 0x0000000800 0x0000000803) [ 1073.201289] radeon 0000:02:00.0: bo 98000001e5dfac00 va 0x0000000802 conflict with (bo 98000001e5dfbc00 0x0000000800 0x0000000803) [ 1073.213795] radeon 0000:02:00.0: bo 98000001e5dfac00 va 0x0000000802 conflict with (bo 98000001e5dfbc00 0x0000000800 0x0000000803) [ 1074.413274] radeon 0000:02:00.0: bo 98000001e5d76800 va 0x0000000802 conflict with (bo 98000001e5d74000 0x0000000800 0x0000000803) [ 1074.425699] radeon 0000:02:00.0: bo 98000001e5d76800 va 0x0000000802 conflict with (bo 98000001e5d74000 0x0000000800 0x0000000803) [ 1075.634164] radeon 0000:02:00.0: bo 98000001fad14c00 va 0x0000000802 conflict with (bo 98000001fad16c00 0x0000000800 0x0000000803) [ 1075.646623] radeon 0000:02:00.0: bo 98000001fad14c00 va 0x0000000802 conflict with (bo 98000001fad16c00 0x0000000800 0x0000000803) [ 1076.867784] radeon 0000:02:00.0: bo 98000001e5dfbc00 va 0x0000000802 conflict with (bo 98000001e5dfb800 0x0000000800 0x0000000803) [ 1076.880201] radeon 0000:02:00.0: bo 98000001e5dfbc00 va 0x0000000802 conflict with (bo 98000001e5dfb800 0x0000000800 0x0000000803) [ 1078.747714] radeon 0000:02:00.0: bo 98000001e5df9400 va 0x0000000802 conflict with (bo 98000001e5df8c00 0x0000000800 0x0000000803) [ 1078.760208] radeon 0000:02:00.0: bo 98000001e5df9400 va 0x0000000802 conflict with (bo 98000001e5df8c00 0x0000000800 0x0000000803) (In reply to Michel Dänzer from comment #3) > Created attachment 119339 [details] [review] [review] > winsys/radeon: Use CPU page size instead of hardcoding 4096 > > Updated patch which leaves the 4K alignment for the VM range start address. I have backport this patch to mesa 10.4.0 and fixed. but i'm not sure the changes in radeon_winsys_bo_from_ptr isn't ok? because buffer_from_ptr missing in mesa 10.4.0. Thanks! Module: Mesa Branch: master Commit: 24abbaff9ad177624c2b4906c7d94f5d91ac3cc0 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=24abbaff9ad177624c2b4906c7d94f5d91ac3cc0 Author: Michel Dänzer <michel.daenzer@amd.com> Date: Thu Aug 21 18:30:44 2014 +0900 winsys/radeon: Use CPU page size instead of hardcoding 4096 bytes v3 |
Use of freedesktop.org services, including Bugzilla, is subject to our Code of Conduct. How we collect and use information is described in our Privacy Policy.