| Summary: |
[Patch] Preserving PCI Burst Write Wait State Select Bit |
| Product: |
xorg
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Reporter: |
Kevin Brace <kevinbrace> |
| Component: |
Driver/openchrome | Assignee: |
Openchrome development list <openchrome-devel> |
| Status: |
RESOLVED
FIXED
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QA Contact: |
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| Severity: |
enhancement
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| Priority: |
medium
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| Version: |
unspecified | |
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| Hardware: |
x86 (IA32) | |
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| OS: |
Linux (All) | |
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| Whiteboard: |
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i915 platform:
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i915 features:
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| Attachments: |
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Created attachment 120329 [details] [Patch] Preserving PCI Burst Write Wait State Select Bit Preserving PCI Burst Write Wait State Select Bit. In the process of trying to debug ACPI S3 State resume bug when an LVDS-based DFP is used, it was discovered that OpenChrome is tinkering with PCI Burst Write Wait State Select bit (0x3c5.0x1a[2]) on its own for no good reasons. Typically, the option to enable 1 wait state PCI transaction in many VIA Technologies chipset-based computers is provided in the BIOS setup, therefore, it is prudent for OpenChrome not to tinker with this bit. Any code references that alter this bit were removed.