| Summary: | [byt] Bad powerwell for display reg read during interrupt handler (valleyview_pipestat_irq_handle) | ||
|---|---|---|---|
| Product: | DRI | Reporter: | Chris Wilson <chris> |
| Component: | DRM/Intel | Assignee: | Intel GFX Bugs mailing list <intel-gfx-bugs> |
| Status: | CLOSED FIXED | QA Contact: | Intel GFX Bugs mailing list <intel-gfx-bugs> |
| Severity: | normal | ||
| Priority: | medium | CC: | intel-gfx-bugs |
| Version: | DRI git | ||
| Hardware: | Other | ||
| OS: | All | ||
| Whiteboard: | |||
| i915 platform: | BYT | i915 features: | power/Other |
|
Description
Chris Wilson
2016-01-16 16:55:13 UTC
Hmm. I wonder why were not getting this all the time. Or are we?
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1651,6 +1651,12 @@ static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
int pipe;
spin_lock(&dev_priv->irq_lock);
+
+ if (!dev_priv->display_irqs_enabled) {
+ spin_unlock(&dev_priv->irq_lock);
+ return;
+ }
+
for_each_pipe(dev_priv, pipe) {
i915_reg_t reg;
u32 mask, iir_bit = 0;
Had to remember that the warning was disabled in -nightly! Patch worksforme. commit 1ca993d237a587be19dd58cfe27f1e9093291320 Author: Ville Syrjälä <ville.syrjala@linux.intel.com> Date: Thu Feb 18 21:54:26 2016 +0200 drm/i915: Skip PIPESTAT reads from irq handler on VLV/CHV when power well is down |
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