Bug 95012

Summary: [SNB] glsl-1_50.execution.built-in-functions.gs-op tests intermittent
Product: Mesa Reporter: Mark Janes <mark.a.janes>
Component: Drivers/DRI/i965Assignee: Ian Romanick <idr>
Status: RESOLVED FIXED QA Contact: Intel 3D Bugs Mailing List <intel-3d-bugs>
Severity: normal    
Priority: medium    
Version: git   
Hardware: Other   
OS: All   
Whiteboard:
i915 platform: i915 features:

Description Mark Janes 2016-04-18 23:35:58 UTC 
SNB sees intermittent tests failures in this category:

piglit.spec.glsl-1_50.execution.built-in-functions.gs-op-rshift-int-uint.snbgt2m64
piglit.spec.glsl-1_50.execution.built-in-functions.gs-op-ne-bvec4-bvec4.snbgt1m32
piglit.spec.glsl-1_50.execution.built-in-functions.gs-op-eq-bvec3-bvec3-using-if.snbgt2m32

sample output:

/tmp/build_root/m64/lib/piglit/bin/shader_runner /tmp/build_root/m64/lib/piglit/generated_tests/spec/glsl-1.50/execution/built-in-functions/gs-op-rshift-int-uint.shader_test -auto
piglit: debug: Requested an OpenGL 3.2 Core Context, and received a matching 3.3 context

Probe color at (192,2)
  Expected: 0.000000 1.000000 0.000000 1.000000
  Observed: 0.000000 0.000000 1.000000 0.000000
Probe color at (196,2)
  Expected: 0.000000 1.000000 0.000000 1.000000
  Observed: 0.000000 0.000000 1.000000 0.000000
Probe color at (200,2)
  Expected: 0.000000 1.000000 0.000000 1.000000
  Observed: 0.000000 0.000000 1.000000 0.000000
Probe color at (204,2)
  Expected: 0.000000 1.000000 0.000000 1.000000
  Observed: 0.000000 0.000000 1.000000 0.000000

Running the test repeatedly by itself will not reproduce the failure.

Tests have been disabled in the CI.
Comment 1 Matt Turner 2016-08-29 22:35:22 UTC 
These tests (as do likely all geometry shaders on Sandybridge) spill. Curro thinks that spilling in the vec4 backend is broken, which is a good hypothesis for why these tests fail intermittently when run in CI.
Comment 2 Ian Romanick 2018-04-24 18:33:25 UTC 
This should be fixed by:

commit 0d5ce25c1ca23abc6d91538f4374a18509091060 (origin/master, origin/HEAD)
Author: Ian Romanick <ian.d.romanick@intel.com>
Date:   Mon Apr 16 16:32:41 2018 -0700

    intel/compiler: Add scheduler deps for instructions that implicitly read g0
    
    Otherwise the scheduler can move the writes after the reads.
    
    Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95009
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95012
    Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
    Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
    Tested-by: Mark Janes <mark.a.janes@intel.com>
    Cc: Clayton A Craft <clayton.a.craft@intel.com>
    Cc: mesa-stable@lists.freedesktop.org

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