Bug 95009 - [SNB] amd_shader_trinary_minmax.execution.built-in-functions.gs-mid3-ivec2-ivec2-ivec2 intermittent
Summary: [SNB] amd_shader_trinary_minmax.execution.built-in-functions.gs-mid3-ivec2-iv...
Status: RESOLVED FIXED
Alias: None
Product: Mesa
Classification: Unclassified
Component: Drivers/DRI/i965 (show other bugs)
Version: git
Hardware: x86-64 (AMD64) Linux (All)
: medium normal
Assignee: Intel 3D Bugs Mailing List
QA Contact: Intel 3D Bugs Mailing List
URL:
Whiteboard:
Keywords:
Depends on:
Blocks:
 
Reported: 2016-04-18 23:25 UTC by Mark Janes
Modified: 2018-04-24 18:33 UTC (History)
0 users

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i915 platform:
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Attachments

Description Mark Janes 2016-04-18 23:25:28 UTC
This test fails intermittently on SNB:

/tmp/build_root/m64/lib/piglit/bin/shader_runner /tmp/build_root/m64/lib/piglit/generated_tests/spec/amd_shader_trinary_minmax/execution/built-in-functions/gs-mid3-ivec2-ivec2-ivec2.shader_test -auto
piglit: debug: Requested an OpenGL 3.2 Core Context, and received a matching 3.3 context

Probe color at (128,4)
  Expected: 0.000000 1.000000 0.000000 1.000000
  Observed: 0.000000 0.000000 1.000000 0.000000
Probe color at (132,4)
  Expected: 0.000000 1.000000 0.000000 1.000000
  Observed: 0.000000 0.000000 1.000000 0.000000
Probe color at (136,4)
  Expected: 0.000000 1.000000 0.000000 1.000000
  Observed: 0.000000 0.000000 1.000000 0.000000
Probe color at (140,4)
  Expected: 0.000000 1.000000 0.000000 1.000000
  Observed: 0.000000 0.000000 1.000000 0.000000

Running it repeatedly on its own does not reproduce the bug.  It has been disabled in Intel's CI.
Comment 1 Matt Turner 2016-08-29 22:35:28 UTC
These tests (as do likely all geometry shaders on Sandybridge) spill. Curro thinks that spilling in the vec4 backend is broken, which is a good hypothesis for why these tests fail intermittently when run in CI.
Comment 2 Ian Romanick 2018-04-24 18:33:02 UTC
This should be fixed by:

commit 0d5ce25c1ca23abc6d91538f4374a18509091060 (origin/master, origin/HEAD)
Author: Ian Romanick <ian.d.romanick@intel.com>
Date:   Mon Apr 16 16:32:41 2018 -0700

    intel/compiler: Add scheduler deps for instructions that implicitly read g0
    
    Otherwise the scheduler can move the writes after the reads.
    
    Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95009
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95012
    Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
    Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
    Tested-by: Mark Janes <mark.a.janes@intel.com>
    Cc: Clayton A Craft <clayton.a.craft@intel.com>
    Cc: mesa-stable@lists.freedesktop.org


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