Created attachment 132150 [details]
SPIR-V vertex shader that uses OpSwitch on a uint64_t (may be incorrect)
I noticed that even though shaderInt64 is true on gen 8 and above, the SPIR-V to NIR translator code doesn't support OpSwitch on 64-bit integers.
Supporting 64-bit integers in OpSwitch requires parsing 2 for each switch value, with the target block id, it requires 3 words for each switch case.
The latest commit on master when I checked is e558a7a9888ee56863f11e7ede387689626f6ea9.
see OpSwitch translation code: https://github.com/mesa3d/mesa/blob/master/src/compiler/spirv/vtn_cfg.c#L400
code that enables shaderInt64:
Note: from what I can tell, glslang doesn't currently allow creating OpSwitch on a int64, so programs that use OpSwitch this way are probably non-existant.
I'm switching this to be a bug in radv because commit 1bc40ae9524477de9d4f73b57b3ae69a40923695 enabled int64 support in radv even though the spir-v to nir translation code hasn't been fixed yet.
Ugh... I guess I didn't read the language on OpSwitch all that carefully the first time around. This is going to be exceedingly painful to do correctly. In order to know the number of switch cases, we have to know the bit size of the selector. However, we need to know the switch cases early when we do the initial CFG walk and, at that point, we haven't processed any instructions other than control-flow so we have no way to know the bit size of the selector.
you could implement an initial type-deduction pass; you shouldn't need to know the cfg for that to work, because the OpPhi instructions state their type.
I have a branch for this now:
This should be fixed by the following commit:
Author: Jason Ekstrand <email@example.com>
Date: Wed Dec 6 10:01:22 2017 -0800
spirv: Add support for all bit sizes in OpSwitch
Reviewed-by: Ian Romanick <firstname.lastname@example.org>