This seems to be covering i965 DRI driver - reassigning.

Building tag 17.2.4 with the below change fixes the problem for me.

diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c
index 5118d96c38..2c9f7d735f 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -239,7 +239,7 @@ brw_clear(struct gl_context *ctx, GLbitfield mask)
          mt->stencil_mt->r8stencil_needs_update = true;
    }
 
-   if (mask & BUFFER_BITS_COLOR) {
+   if (brw->gen >= 6 && (mask & BUFFER_BITS_COLOR)) {
       brw_blorp_clear_color(brw, fb, mask, partial_clear,
                             ctx->Color.sRGBEnabled);
       debug_mask("blorp color", mask & BUFFER_BITS_COLOR);

The bisection is

commit 79f2a5541f92920d35d3621179f7377c97cc75e1
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date:   Fri May 12 17:14:18 2017 -0700

    i965: Use BLORP for color clears on gen4-5

Wondering if we couldn't merge the hunk in comment 2 (alongside a reference to this bug). It will address the mpv crash and we can resolve properly at a later stage?

Hello!

I was able to reproduce GPU hangs on Ironlake using mpv -hwdec=vaapi, and I believe I have a fix: https://patchwork.freedesktop.org/patch/188597/

If possible, could you try the patch and see if it fixes it for you?

If it doesn't work, could you please attach /sys/class/drm/card0/error to the bug report?

Thanks!
--Ken

Kenneth, your patch fixes the issue for me (on 17.2.4).

Fixed on master by:

commit 8f91aa35a54e127b68415376ef2b577ea8fc30f9
Author: Kenneth Graunke <kenneth@whitecape.org>
Date:   Wed Nov 15 22:40:16 2017 -0800

    i965: Upload invariant state once at the start of the batch on Gen4-5.
    
    We want to emit invariant state at the start of a render batch.  In the
    past, this more or less happened: a new batch flagged BRW_NEW_CONTEXT
    (because we don't have hardware contexts), which triggered the
    brw_invariant_state atom.  So, it would be emitted before any 3D
    drawing.  (Technically, there might be some BLT commands in the batch
    because Gen4-5 have a single combined render/BLT ring, but that should
    be harmless).
    
    With the advent of BLORP, this broke.  The first item in a batch might
    be a BLORP operation, which bypasses the normal draw upload path.  So,
    we need to ensure invariant state happens first.  To do that, we just
    upload it when creating a new batch.  On Gen6+ we'd need to worry about
    whether it's a RENDER or BLT batch, but because we have a combined ring,
    this approach should work fine on Gen4-5.
    
    Seems to fix GPU hangs when playing hardware accelerated video with
    mpv -hwdec=vaapi on Ironlake.
    
    Cc: mesa-stable@lists.freedesktop.org
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103529
    Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

Hopefully it should arrive in the stable branches soon.