https://intel-gfx-ci.01.org/tree/drm-tip/IGT_4113/shard-glkb4/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html <7>[40087.920681] [IGT] kms_cursor_legacy: starting subtest basic-flip-before-cursor-varying-size <7>[40087.920973] [drm:drm_mode_addfb2] [FB:98] <7>[40087.933596] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010 <7>[40087.933639] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long <7>[40087.933676] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1 <7>[40087.933777] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A <3>[40087.934420] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe A FIFO underrun <7>[40087.934968] [drm:intel_fbc_underrun_work_fn [i915]] Disabling FBC due to FIFO underrun.
Is this reproducible when booting with nvme_core.default_ps_max_latency_us=0 module parameter?
(In reply to Jani Nikula from comment #1) > Is this reproducible when booting with nvme_core.default_ps_max_latency_us=0 > module parameter? This has so far happened 1/121 runs, so I don't think changing to nvme_core.default_ps_max_latency_us=0 will give any noticable effect.
Last seen IGT_4113: 2018-01-04 / 230 runs ago
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