https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_3671/shard-glkb3/igt@kms_frontbuffer_tracking@fbc-1p-rte.html

<7>[  156.508921] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
<7>[  156.508960] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
<7>[  156.509002] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000068
<7>[  156.509074] [drm:wait_panel_status [i915]] Wait complete
<7>[  156.509112] [drm:edp_panel_on [i915]] Wait for panel power on
<7>[  156.509153] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 0000000a control 0000006b
<7>[  156.711752] [drm:wait_panel_status [i915]] Wait complete
<7>[  156.711800] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well
<7>[  156.713144] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
<7>[  156.713207] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
<7>[  156.713273] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
<7>[  156.714156] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
<7>[  156.714216] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
<7>[  156.715025] [drm:intel_dp_start_link_train [i915]] clock recovery OK
<7>[  156.715134] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
<7>[  156.716278] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
<7>[  156.716335] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
<7>[  156.717560] [drm:intel_dp_dump_link_status [i915]] ln0_1:0x66 ln2_3:0x66 align:0x81 sink:0x0 adj_req0_1:0x44 adj_req2_3:0x44
<7>[  156.717622] [drm:intel_dp_start_link_train [i915]] Clock recovery check failed, cannot continue channel equalization
<3>[  156.717686] [drm:intel_dp_start_link_train [i915]] *ERROR* [CONNECTOR:77:eDP-1] Link Training failed at link rate = 540000, lane count = 4