I'm hitting following assert in compiler with the attached shader_test and bisected this to commit ee63933a73:
shader_runner: ../src/intel/compiler/brw_eu_emit.c:822: brw_alu3: Assertion `dest.file == BRW_GENERAL_REGISTER_FILE || dest.file == BRW_MESSAGE_REGISTER_FILE' failed.
Created attachment 138306 [details]
Attaching shader test. Original use-case was just vs+gs moving particles but I added here a fs so that issuing a draw will trigger the case.
Does this only occur on HSW? I was not able to reproduce the problem with this test case on my BDW.
Interesting side note: This shader is hurt by 1 instruction by this optimization.
(In reply to Ian Romanick from comment #2)
> Does this only occur on HSW? I was not able to reproduce the problem with
> this test case on my BDW.
Yes, sorry I did not remember to mention this but I tried also on KBL and could not reproduce it. So it is very likely HSW (+IVB?) specific. It could be that there is some 'hidden' issue we've found here.
After this change, it seems that the backend is trying to emit something like
mad.l.f0 null, ...
But 3 source instructions cannot write the null register. Matt says fixup_3src_null_dest handles this for the fs backend.
Author: Ian Romanick <firstname.lastname@example.org>
Date: Fri Mar 23 11:46:12 2018 -0700
i965/vec4: Fix null destination register in 3-source instructions
A recent commit (see below) triggered some cases where conditional
modifier propagation and dead code elimination would cause a MAD
instruction like the following to be generated:
mad.l.f0 null, ...
Matt pointed out that fs_visitor::fixup_3src_null_dest() fixes cases
like this in the scalar backend. This commit basically ports that code
to the vec4 backend.
NOTE: I have sent a couple tests to the piglit list that reproduce this
bug *without* the commit mentioned below. This commit fixes those
Signed-off-by: Ian Romanick <email@example.com>
Reviewed-by: Matt Turner <firstname.lastname@example.org>
Tested-by: Tapani Pälli <email@example.com>
Fixes: ee63933a7 ("nir: Distribute binary operations with constants into bcsel")