Intel-GFX-CI hosts are starting to run i915 selftests, and this bug is part of the series "Initial findings" GDG and CTG fail at drv_selftest@live_objects with: [ 440.580921] Setting dangerous option live_selftests - tainting kernel [ 441.169235] Partial view for 1 [1] (offset=0, size=256 [256, row size 64], fence=0, tiling=2, stride=8192) misalignment, expected write to page (32 + 0 [0x20000]) of 0x1, found 0xb00 [ 441.169348] i915/i915_gem_object_live_selftests: igt_partial_tiling failed with error -22 [ 441.256024] i915: probe of 0000:00:02.0 failed with error -22 Full traces at: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4432/fi-gdg-551/igt@drv_selftest@live_objects.html https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4433/fi-ctg-p8600/igt@drv_selftest@live_objects.html
Note, both ctg and gdg have unknown swizzling due to irregular memory layout, but I bet I also skipped a corner on implementing !128-byte Y-tiling swizzling.
commit 73d8e5fba54f400cd5fe48517dbe6776fb16c2ad Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Thu Jul 5 18:15:23 2018 +0100 drm/i915/selftests: Detect unknown swizzling correctly i915_gem_detect_bit_6_swizzle() tries to hide unknown swizzling from userspace (and ourselves) leaving us with the only clue inside i915->quirks & QUIRK_PIN_SWIZZLED_PAGES. If we see this bit set, it means that we really have no clue as to what the swizzle pattern is being used in any one page and so cannot compute what the reference value should be in our tiling selftests. We have to skip the test. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107133 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180705171523.18462-1-chris@chris-wilson.co.uk
This is still happening on gdg: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_4460/fi-gdg-551/igt@drv_selftest@live_objects.html [ 412.922361] Setting dangerous option live_selftests - tainting kernel [ 414.202627] Partial view for 1 [1] (offset=0, size=256 [256, row size 64], fence=0, tiling=2, stride=8192) misalignment, expected write to page (8 + 0 [0x8000]) of 0x1, found 0x4b0b0273 [ 414.202848] i915/i915_gem_object_live_selftests: igt_partial_tiling failed with error -22 [ 414.291040] i915: probe of 0000:00:02.0 failed with error -22
commit cecb368d2fe40e7f6a8166fef35abc69852f7501 Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Mon Jul 9 20:49:15 2018 +0100 drm/i915/selftests: Filter out both physical address swizzles In our swizzling selftests, we cannot predict the physical address of the target page (at least not simply!) and so skip bit17 swizzles. However, there are two bit17 swizzle modes and we only skipped one, with the second being observed on the lab gdg causing the test to fail, as soon as we hit a page with bit17 set in its address. Testcase: igt/drv_selftest/live_objects #gdg Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180709194915.5789-1-chris@chris-wilson.co.uk
Can we confirm fixed so that the issue can be closed?
This issue has been fixed in DRM-Tip for GD and CTG, can be seen at https://intel-gfx-ci.01.org/tree/drm-tip/igt@drv_selftest@live_objects.html
Closing as per Tomi's confirmation
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