https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_93/fi-icl-u/igt@gem_workarounds@basic-read-context.html

(gem_workarounds:1219) WARNING: 0x0E420	0x00100010	0x00000010	0x00000000	FAIL
(gem_workarounds:1219) CRITICAL: Test assertion failure function check_workarounds, file ../tests/gem_workarounds.c:191:
(gem_workarounds:1219) CRITICAL: Failed assertion: workaround_fail_count(fd, ctx) == 0
(gem_workarounds:1219) CRITICAL: error: 1 != 0
Subtest basic-read-context failed.

commit c358514ba8da9e235876db1628cedd19a35803c6
Author: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Date:   Mon Jul 30 15:06:36 2018 +0300

    Revert "drm/i915/icl: WaEnableFloatBlendOptimization"
    
    The register for 0xe420 is unable to hold any value, including
    this bit. The documentation is also mixed between having a
    register bit for toggle and having a state command setup
    for it. Apparently the register toggle is deprecated.
    
    Remove the register toggle as evidence shows it's futile.
    
    The thing remaining is an apology and humble request for
    Mesa folks to resurrect their state setup for this as they
    were on right track from start.
    
    This reverts commit 0bf059f3532bb39c52d917142206a8554fc2f1c5.
    
    Fixes: 0bf059f3532b ("drm/i915/icl: WaEnableFloatBlendOptimization")
    References: HSDES#1406393558
    Cc: Oscar Mateo <oscar.mateo@intel.com>
    Cc: Anuj Phogat <anuj.phogat@gmail.com>
    Cc: Chris Wilson <chris@chris-wilson.co.uk>
    Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
    Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
    Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
    Link: https://patchwork.freedesktop.org/patch/msgid/20180730120636.26958-1-mika.kuoppala@linux.intel.com

Closing, not seen since 4 weeks.

After investigating this issue, it appears that the register is holding the value to set WaEnableFloatBlendOptimization. The issue is that HW currently does not have this register muxed to be read. This test reads bit4 to check if the WA is enabled but returns 0 for the aforementioned reason.

For ICL, the register is used to enable this feature and remains so. This will only move to a state cmd for next gen.

Can we merge back the patch that was reverted?

Wondering if this should still be highest priority though?

(In reply to Talha Nassar from comment #4)
> After investigating this issue, it appears that the register is holding the
> value to set WaEnableFloatBlendOptimization. The issue is that HW currently
> does not have this register muxed to be read. This test reads bit4 to check
> if the WA is enabled but returns 0 for the aforementioned reason.
> 
> For ICL, the register is used to enable this feature and remains so. This
> will only move to a state cmd for next gen.
> 
> Can we merge back the patch that was reverted?

Submit a patch to set the register and *not* mark it as being required for read back by the test.

Reducing the priority as this issue was not occurring currently, can be raised if this happens again due to merging the reverted changes.

Talha, any updates here?

Both IGT and kernel patches were submitted. IGT patch adds the register to WO list. Kernel patch enables the WA.
However, I worked on Chris' suggestion to update the WA itself to work with self-tests. Pending is to check to make sure the WA is actually enabled before submitting the patch again.

Talha, Is the WA enabled? Any update on changes to WA?

The patch is submitted. Will update once merged.

Patch got merged.
Thank you Chris!