Bug 107345 - [CI][DRMTIP] igt@* - dmesg-warn - *ERROR* DPLL 1 not locked
Summary: [CI][DRMTIP] igt@* - dmesg-warn - *ERROR* DPLL 1 not locked
Status: NEW
Alias: None
Product: DRI
Classification: Unclassified
Component: DRM/Intel (show other bugs)
Version: XOrg git
Hardware: Other All
: medium normal
Assignee: Intel GFX Bugs mailing list
QA Contact: Intel GFX Bugs mailing list
URL:
Whiteboard: ReadyForDev
Keywords:
Depends on:
Blocks:
 
Reported: 2018-07-23 15:27 UTC by Martin Peres
Modified: 2019-08-29 22:17 UTC (History)
1 user (show)

See Also:
i915 platform: CFL
i915 features: display/Other


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Description Martin Peres 2018-07-23 15:27:19 UTC
https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_76/fi-cfl-8109u/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html

[drm:intel_enable_shared_dpll [i915]] *ERROR* DPLL 1 not locked
Comment 1 Matt Roper 2019-08-29 22:17:32 UTC
This bug is seen only rarely (~2% of runs); the last occurrence was two weeks ago.  It can occur during pretty much any IGT test on the fi-cfl-8109u machine.

The issue here arises when we're enabling DPLL1; as part of the enable sequence we're supposed to wait for the DPLL lock status to appear in the DPLL_STATUS register.  For gen9 big core platforms, the bspec doesn't tell us how long we're supposed to wait the pll to lock before declaring a timeout, so we're reusing the same 5ms timeout that the bspec suggested for BDW.  It seems possible that BDW's 5ms timeout might not be enough in some cases on gen9, so we should probably try bumping it up a bit to see if there's any impact on the CI results.

I've submitted a patch here that will bump up the timeout:
https://patchwork.freedesktop.org/series/66025/


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