[drm:intel_enable_shared_dpll [i915]] *ERROR* DPLL 1 not locked
This bug is seen only rarely (~2% of runs); the last occurrence was two weeks ago. It can occur during pretty much any IGT test on the fi-cfl-8109u machine.
The issue here arises when we're enabling DPLL1; as part of the enable sequence we're supposed to wait for the DPLL lock status to appear in the DPLL_STATUS register. For gen9 big core platforms, the bspec doesn't tell us how long we're supposed to wait the pll to lock before declaring a timeout, so we're reusing the same 5ms timeout that the bspec suggested for BDW. It seems possible that BDW's 5ms timeout might not be enough in some cases on gen9, so we should probably try bumping it up a bit to see if there's any impact on the CI results.
I've submitted a patch here that will bump up the timeout:
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