https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_92/fi-byt-j1900/igt@gem_exec_parallel@blt-fds.html https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_93/fi-byt-j1900/igt@gem_exec_parallel@blt-fds.html (gem_exec_parallel:1259) CRITICAL: Test assertion failure function check_bo, file ../tests/gem_exec_parallel.c:54: (gem_exec_parallel:1259) CRITICAL: Failed assertion: map[i] == i (gem_exec_parallel:1259) CRITICAL: error: 0 != 583
Same suspect as commit 70b73f9ac113983f9c7db9887447f1344ac5b69b Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Thu Aug 30 17:10:42 2018 +0100 drm/i915/ringbuffer: Delay after invalidating gen6+ xcs During stress testing of full-ppgtt (on Baytrail at least), we found that the invalidation around a context/mm switch was insufficient (writes would go astray). Adding a second MI_FLUSH_DW barrier prevents this, but it is unclear as to whether this is merely a delaying tactic or if it is truly serialising with the TLB invalidation. Either way, it is empirically required. v2: Avoid the loop for readability; Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107715 References: https://bugs.freedesktop.org/show_bug.cgi?id=107759 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Matthew Auld <matthew.william.auld@gmail.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180830161042.29193-1-chris@chris-wilson.co.uk As with the others, lets see what happens now.
(In reply to Chris Wilson from comment #1) > Same suspect as > > commit 70b73f9ac113983f9c7db9887447f1344ac5b69b > Author: Chris Wilson <chris@chris-wilson.co.uk> > Date: Thu Aug 30 17:10:42 2018 +0100 > > drm/i915/ringbuffer: Delay after invalidating gen6+ xcs > > During stress testing of full-ppgtt (on Baytrail at least), we found > that the invalidation around a context/mm switch was insufficient (writes > would go astray). Adding a second MI_FLUSH_DW barrier prevents this, but > it is unclear as to whether this is merely a delaying tactic or if it is > truly serialising with the TLB invalidation. Either way, it is > empirically required. > > v2: Avoid the loop for readability; > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107715 > References: https://bugs.freedesktop.org/show_bug.cgi?id=107759 > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> > Cc: Matthew Auld <matthew.william.auld@gmail.com> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > Link: > https://patchwork.freedesktop.org/patch/msgid/20180830161042.29193-1- > chris@chris-wilson.co.uk > > As with the others, lets see what happens now. Looks like it fixed it! It uised to happen almost every run, and now nothing in 10 runs. Closing!
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