https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5022/shard-glk7/igt@gem_ctx_isolation@rcs0-dirty-switch.html Starting subtest: rcs0-dirty-switch (gem_ctx_isolation:5586) WARNING: Register 0x2158 (BB_OFFSET): A=00000001 B=00000005 (gem_ctx_isolation:5586) CRITICAL: Test assertion failure function compare_regs, file ../tests/i915/gem_ctx_isolation.c:474: (gem_ctx_isolation:5586) CRITICAL: Failed assertion: num_errors == 0 (gem_ctx_isolation:5586) CRITICAL: 1 registers mistached between two reads of the same ctx. Subtest rcs0-dirty-switch failed.
Lalalalalala. Wait and see; it might be a sampling issue and that we need a CS stall around the SRM, or hopefully more likely it will never happen again.
Still seen once in a month.
Setting to NEEDINFO as we wait for this to happen again.
commit 478452fece3997dfacaa4d6babe6b8bf6fef784f (upstream/master, origin/master, origin/HEAD) Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Mon Jan 7 12:35:27 2019 +0000 i915/gem_ctx_isolation: Ignore the low bits of BB_OFFSET On Skylake, BB_OFFSET seems to be unstable. Since this is an offset into the batch at the time of CS execution, it should be actively written to as we read from the register so allow it a qword of discrepancy (since the CS should be reading in qwords). This still allows us to detect dirt across the rest of the register field, should that be required. v2: restrict ignore_bits to only BIT(2) that we see fluctuate in testing (Antonio) Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Antonio Argenziano <antonio.argenziano@intel.com>
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