Bug 108536 - [CI][SHARDS] igt@gem_ctx_isolation@rcs0-dirty-switch - fail - Failed assertion: num_errors == 0
Summary: [CI][SHARDS] igt@gem_ctx_isolation@rcs0-dirty-switch - fail - Failed assertio...
Status: CLOSED WORKSFORME
Alias: None
Product: DRI
Classification: Unclassified
Component: DRM/Intel (show other bugs)
Version: XOrg git
Hardware: Other All
: high normal
Assignee: Intel GFX Bugs mailing list
QA Contact: Intel GFX Bugs mailing list
URL:
Whiteboard: ReadyForDev
Keywords:
Depends on:
Blocks:
 
Reported: 2018-10-24 10:48 UTC by Martin Peres
Modified: 2019-02-14 16:21 UTC (History)
1 user (show)

See Also:
i915 platform: GLK
i915 features: GEM/Other


Attachments

Note You need to log in before you can comment on or make changes to this bug.
Description Martin Peres 2018-10-24 10:48:18 UTC
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5022/shard-glk7/igt@gem_ctx_isolation@rcs0-dirty-switch.html

Starting subtest: rcs0-dirty-switch
(gem_ctx_isolation:5586) WARNING: Register 0x2158 (BB_OFFSET): A=00000001 B=00000005
(gem_ctx_isolation:5586) CRITICAL: Test assertion failure function compare_regs, file ../tests/i915/gem_ctx_isolation.c:474:
(gem_ctx_isolation:5586) CRITICAL: Failed assertion: num_errors == 0
(gem_ctx_isolation:5586) CRITICAL: 1 registers mistached between two reads of the same ctx.
Subtest rcs0-dirty-switch failed.
Comment 1 Chris Wilson 2018-10-24 11:33:27 UTC
Lalalalalala. Wait and see; it might be a sampling issue and that we need a CS stall around the SRM, or hopefully more likely it will never happen again.
Comment 2 Francesco Balestrieri 2018-11-28 08:39:40 UTC
Still seen once in a month.
Comment 3 Francesco Balestrieri 2018-11-28 08:41:25 UTC
Setting to NEEDINFO as we wait for this to happen again.
Comment 4 Chris Wilson 2019-01-10 23:33:09 UTC
commit 478452fece3997dfacaa4d6babe6b8bf6fef784f (upstream/master, origin/master, origin/HEAD)
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Mon Jan 7 12:35:27 2019 +0000

    i915/gem_ctx_isolation: Ignore the low bits of BB_OFFSET
    
    On Skylake, BB_OFFSET seems to be unstable. Since this is an
    offset into the batch at the time of CS execution, it should be actively
    written to as we read from the register so allow it a qword of
    discrepancy (since the CS should be reading in qwords). This still
    allows us to detect dirt across the rest of the register field, should
    that be required.
    
    v2: restrict ignore_bits to only BIT(2) that we see fluctuate in testing
    (Antonio)
    
    Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
    Reviewed-by: Antonio Argenziano <antonio.argenziano@intel.com>
Comment 5 CI Bug Log 2019-02-14 16:21:16 UTC
The CI Bug Log issue associated to this bug has been archived.

New failures matching the above filters will not be associated to this bug anymore.


Use of freedesktop.org services, including Bugzilla, is subject to our Code of Conduct. How we collect and use information is described in our Privacy Policy.