The priority is set to high because the guc is not used in production.

A simple solution would be to accept that guc preemption is not yet functional.

--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -1285,6 +1285,7 @@ static void guc_set_default_submission(struct intel_engine_cs *engine)
        engine->reset.prepare = guc_reset_prepare;
 
        engine->flags &= ~I915_ENGINE_SUPPORTS_STATS;
+       engine->flags &= ~I915_ENGINE_HAS_PREEMPTION;
 }
 
 int intel_guc_submission_enable(struct intel_guc *guc)

*** Bug 108732 has been marked as a duplicate of this bug. ***

https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_145/fi-apl-guc/igt@runner@aborted.html

Aborting.
Previous test: i915_hangman (hangcheck-unterminated)
Next test: gem_exec_params (rel-constants-invalid)

Kernel tainted (0x240 -- 200)

Test result of igt@i915_hangman@hangcheck-unterminated is pass.

https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_145/fi-apl-guc/igt%40i915_hangman%40hangcheck-unterminated.html

Issue reported on BXT part with boot parameter i915.enable_guc=3, which means submission via guc enabled. Further investigation will be deferred until after upcoming update to guc version and only if issue seen with i915.enable_guc=2 (no submission via GuC) which is support model for Gen9.

(In reply to Jon Ewins from comment #5)
> Issue reported on BXT part with boot parameter i915.enable_guc=3, which
> means submission via guc enabled. Further investigation will be deferred
> until after upcoming update to guc version and only if issue seen with
> i915.enable_guc=2 (no submission via GuC) which is support model for Gen9.

Of course it won't be seen with enable_guc=2, the issue is that preemption is broken via the guc! I take it we should just remove the unstable unsupported feature from the guc submission path?

Agreed, this was too generic an update for this particular bug.  We are about to upstream new patches for Gen9 and Gen11 that support a changed unified interface to the GuC along with the corresponding firmware and so are deferring further actions on current guc issues.  In this specific case, the existing Gen9 guc preemption paths are no longer required and GuC submission on gen9 will not be supported. The imminent new guc code patches will initially disable preemption with guc, but not touch/remove this code. Follow up patches will reinstate GuC based preemption for Gen11+, at which time this code will be cleaned up.  Certainly some of the current code can be cleaned up now, but How the new preemption implementation will be staged in terms of H2G interactions is tbd.

commit a2904ade3dc28cf1a1b7deded41f4369f75e664c
Author: Michal Wajdeczko <michal.wajdeczko@intel.com>
Date:   Mon May 27 18:35:58 2019 +0000

    drm/i915/guc: Don't allow GuC submission
    
    Due to the upcoming changes to the GuC ABI interface, we must
    disable GuC submission mode until final ABI will be available
    on all GuC firmwares.
    
    To avoid regressions on systems configured to run with no longer
    supported configuration "enable_guc=3" or "enable_guc=1" clear
    GuC submission bit.
    
    v2: force switch to non-GuC submission mode
    v3: use GEM_BUG_ON (Joonas)
    
    Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
    Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
    Cc: Chris Wilson <chris@chris-wilson.co.uk>
    Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
    Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
    Cc: John Spotswood <john.a.spotswood@intel.com>
    Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
    Cc: Tony Ye <tony.ye@intel.com>
    Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
    Cc: Jeff Mcgee <jeff.mcgee@intel.com>
    Cc: Antonio Argenziano <antonio.argenziano@intel.com>
    Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
    Cc: Martin Peres <martin.peres@linux.intel.com>
    Acked-by: Martin Peres <martin.peres@linux.intel.com>
    Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
    Link: https://patchwork.freedesktop.org/patch/msgid/20190527183613.17076-3-michal.wajdeczko@intel.com

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