Bug 109198 - [CI][DRMTIP] igt@gem_eio@unwedge-stress - fail - Failed assertion: elapsed < 250e6
Summary: [CI][DRMTIP] igt@gem_eio@unwedge-stress - fail - Failed assertion: elapsed < ...
Alias: None
Product: DRI
Classification: Unclassified
Component: DRM/Intel (show other bugs)
Version: XOrg git
Hardware: Other All
: medium normal
Assignee: Intel GFX Bugs mailing list
QA Contact: Intel GFX Bugs mailing list
Whiteboard: ReadyForDev
Depends on:
Reported: 2018-12-31 15:06 UTC by Martin Peres
Modified: 2019-01-16 07:38 UTC (History)
1 user (show)

See Also:
i915 platform: CFL
i915 features: GEM/Other


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Description Martin Peres 2018-12-31 15:06:17 UTC

Starting subtest: unwedge-stress
(gem_eio:2145) CRITICAL: Test assertion failure function check_wait, file ../tests/i915/gem_eio.c:258:
(gem_eio:2145) CRITICAL: Failed assertion: elapsed < 250e6
(gem_eio:2145) CRITICAL: Wake up following reset+wedge took 252.632ms
Subtest unwedge-stress failed.
Comment 1 CI Bug Log 2018-12-31 15:06:51 UTC
The CI Bug Log issue associated to this bug has been updated.

### New filters associated

* CFL: igt@gem_eio@unwedge-stress - fail - Failed assertion: elapsed &lt; 250e6
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_174/fi-cfl-8109u/igt@gem_eio@unwedge-stress.html
Comment 2 Chris Wilson 2018-12-31 15:14:18 UTC
The 250ms was a number plucked out of thin air. To perform a device reset takes around 10us, so I considered 250ms to have plenty of safety margin built in. In many ways, not being able to reset and restore control within a frame is a failure. So... I don't think I want to raise the timeout (with the exception of say pre-Ironlake where the display engine needs a couple of modesets) and keep looking for a likely root cause behind the occasional delay.
Comment 3 Chris Wilson 2019-01-01 22:42:49 UTC
In this particular case, the delay corresponds to a pcieport error and a very slow timer interrupt.

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