Radv and Anv are affected. Nir optimizations appear to flip ordered/unordered comparisons. Removing ~inot optimization from https://gitlab.freedesktop.org/mesa/mesa/blob/add5a2ec92f4b3f7ac8353e5986dc04186a7b6da/src/compiler/nir/nir_opt_algebraic.py#L160 fixes the vkd3d test failures. See https://lists.freedesktop.org/archives/mesa-dev/2018-December/210780.html for a related discussion. The problem produces the following test failures on Anv: d3d12:8258:31:if_return: Test failed: Got {0.00000000e+00, 0.00000000e+00, 0.00000000e+00, 0.00000000e+00}, expected {1.00000000e+00, 0.00000000e+00, 0.00000000e+00, 0.00000000e+00} at (0, 0). d3d12:8258:41:if_return: Test failed: Got {1.00000000e+00, 1.00000000e+00, 1.00000000e+00, 0.00000000e+00}, expected {1.00000000e+00, 1.00000000e+00, 1.00000000e+00, 1.00000000e+00} at (0, 0). d3d12:8258:48:if_return: Test failed: Got {0.00000000e+00, 0.00000000e+00, 0.00000000e+00, 0.00000000e+00}, expected {1.00000000e+00, 1.00000000e+00, 1.00000000e+00, 1.00000000e+00} at (0, 0). and the following test failures on Radv: d3d12:8258:31:if_return: Test failed: Got {0.00000000e+00, 0.00000000e+00, 0.00000000e+00, 0.00000000e+00}, expected {1.00000000e+00, 0.00000000e+00, 0.00000000e+00, 0.00000000e+00} at (0, 0). d3d12:8258:34:if_return: Test failed: Got {1.00000000e+00, 0.00000000e+00, 0.00000000e+00, 0.00000000e+00}, expected {1.00000000e+00, 1.00000000e+00, 1.00000000e+00, 0.00000000e+00} at (0, 0). d3d12:8258:37:if_return: Test failed: Got {1.00000000e+00, 1.00000000e+00, 0.00000000e+00, 0.00000000e+00}, expected {1.00000000e+00, 1.00000000e+00, 1.00000000e+00, 0.00000000e+00} at (0, 0). d3d12:8258:41:if_return: Test failed: Got {1.00000000e+00, 1.00000000e+00, 1.00000000e+00, 0.00000000e+00}, expected {1.00000000e+00, 1.00000000e+00, 1.00000000e+00, 1.00000000e+00} at (0, 0). d3d12:8258:48:if_return: Test failed: Got {0.00000000e+00, 0.00000000e+00, 0.00000000e+00, 0.00000000e+00}, expected {1.00000000e+00, 1.00000000e+00, 1.00000000e+00, 1.00000000e+00} at (0, 0).
One other solution is to set the exact bit when translating spirv to nir.
+idr. There has been some discussion of this and some different patches on the mailing list for different approaches to solving the problem. This one gets a bit sticky because it's an area where GL is intentionally lax but Vulkan is supposedly more strict. It's also an area where breaking IEEE a little is extremely useful for optimization.
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