Bug 109454 - [CI][DRMTIP] igt@kms_psr@psr2_* - fail - Failed assertion: psr_wait_entry_if_enabled(data)
Summary: [CI][DRMTIP] igt@kms_psr@psr2_* - fail - Failed assertion: psr_wait_entry_if_...
Status: NEW
Alias: None
Product: DRI
Classification: Unclassified
Component: DRM/Intel (show other bugs)
Version: XOrg git
Hardware: Other All
: medium normal
Assignee: Jose Roberto de Souza
QA Contact: Intel GFX Bugs mailing list
URL:
Whiteboard: ReadyForDev
Keywords:
Depends on:
Blocks:
 
Reported: 2019-01-25 09:52 UTC by Martin Peres
Modified: 2019-10-24 01:51 UTC (History)
3 users (show)

See Also:
i915 platform: CFL
i915 features: display/PSR


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Description Martin Peres 2019-01-25 09:52:16 UTC
https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_197/fi-whl-u/igt@kms_psr@psr2_dpms.html

Starting subtest: psr2_dpms
(kms_psr:1510) CRITICAL: Test assertion failure function test_setup, file ../tests/kms_psr.c:394:
(kms_psr:1510) CRITICAL: Failed assertion: psr_wait_entry_if_enabled(data)
Subtest psr2_dpms failed.
Comment 1 Martin Peres 2019-01-25 09:58:35 UTC
I understand users should not care, but I believe this is a little silly for the kernel not to tell IGT that PSR2 is unreachable through debugfs.

What do you think?

PS: This does not mean CI should not move to a PSR2-compatible panel for this gen.
Comment 2 Martin Peres 2019-01-25 09:59:09 UTC
/me just don't like failures in IGT that can be expected
Comment 3 CI Bug Log 2019-01-25 10:00:29 UTC
The CI Bug Log issue associated to this bug has been updated.

### New filters associated

* fi-whl-u: igt@kms_psr@psr2_* - fail - Failed assertion: psr_wait_entry_if_enabled(data)
  - https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2276/fi-whl-u/igt@kms_psr@psr2_primary_page_flip.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2276/fi-whl-u/igt@kms_psr@psr2_cursor_plane_move.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2276/fi-whl-u/igt@kms_psr@psr2_sprite_plane_onoff.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2276/fi-whl-u/igt@kms_psr@psr2_primary_mmap_gtt.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_197/fi-whl-u/igt@kms_psr@psr2_dpms.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_197/fi-whl-u/igt@kms_psr@psr2_suspend.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_197/fi-whl-u/igt@kms_psr@psr2_primary_blt.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_197/fi-whl-u/igt@kms_psr@psr2_basic.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_197/fi-whl-u/igt@kms_psr@psr2_sprite_plane_move.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_197/fi-whl-u/igt@kms_psr@psr2_cursor_plane_move.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_197/fi-whl-u/igt@kms_psr@psr2_cursor_mmap_cpu.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_197/fi-whl-u/igt@kms_psr@psr2_primary_mmap_cpu.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_197/fi-whl-u/igt@kms_psr@psr2_sprite_blt.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_197/fi-whl-u/igt@kms_psr@psr2_sprite_mmap_cpu.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_197/fi-whl-u/igt@kms_psr@psr2_sprite_mmap_gtt.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_197/fi-whl-u/igt@kms_psr@psr2_cursor_render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_197/fi-whl-u/igt@kms_psr@psr2_primary_render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_197/fi-whl-u/igt@kms_psr@psr2_primary_page_flip.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_197/fi-whl-u/igt@kms_psr@psr2_no_drrs.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_197/fi-whl-u/igt@kms_psr@psr2_cursor_blt.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_197/fi-whl-u/igt@kms_psr@psr2_sprite_plane_onoff.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_197/fi-whl-u/igt@kms_psr@psr2_sprite_render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_197/fi-whl-u/igt@kms_psr@psr2_cursor_plane_onoff.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_197/fi-whl-u/igt@kms_psr@psr2_cursor_mmap_gtt.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_197/fi-whl-u/igt@kms_psr@psr2_primary_mmap_gtt.html
Comment 4 CI Bug Log 2019-01-25 13:03:35 UTC
The CI Bug Log issue associated to this bug has been updated.

### New filters associated

* ICL: igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy - dmesg-fail - Poison overwritten
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_191/fi-icl-u3/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
Comment 5 Lakshmi 2019-01-25 13:08:13 UTC
(In reply to CI Bug Log from comment #4)
> The CI Bug Log issue associated to this bug has been updated.
> 
> ### New filters associated
> 
> * ICL: igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy - dmesg-fail -
> Poison overwritten
>   -
> https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_191/fi-icl-u3/
> igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html

This failure is reported in Bug 109458 but not 109454. CI buglog filter is updated again.
Comment 6 Jose Roberto de Souza 2019-01-25 21:00:42 UTC
Hi Martin

Me and Vivi also thinks that make IGT aware of that, we are discussing the solution but like you said it still would be good have some PSR2 coverage in GEN9 hardware.
Comment 7 Matt Roper 2019-10-23 15:26:47 UTC
All failures attached to this bug are on the fi-whl-u machine and from the logs it appears the panel on this machine is considered unreliable:

  <7> [264.149232] [drm:intel_dp_compute_config [i915]] PSR sink implementation is not reliable

which causes the driver to force PSR support off.  IGT is just looking for the string "Sink support: yes [0x03]" in debugfs to know whether a panel support PSR2 or not, but maybe we should also expose the unreliable panel flag through debugfs too and have IGT also confirm that that flag is not set before attempting the test?
Comment 8 Jose Roberto de Souza 2019-10-23 20:41:37 UTC
(In reply to Matt Roper from comment #7)
> All failures attached to this bug are on the fi-whl-u machine and from the
> logs it appears the panel on this machine is considered unreliable:
> 
>   <7> [264.149232] [drm:intel_dp_compute_config [i915]] PSR sink
> implementation is not reliable
> 
> which causes the driver to force PSR support off.  IGT is just looking for
> the string "Sink support: yes [0x03]" in debugfs to know whether a panel
> support PSR2 or not, but maybe we should also expose the unreliable panel
> flag through debugfs too and have IGT also confirm that that flag is not set
> before attempting the test?

Yeah I think is time to have something like this, thanks Matt.


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