https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_181/fi-apl-guc/igt@gem_ctx_isolation@rcs0-none.html Starting subtest: rcs0-none (gem_ctx_isolation:1166) WARNING: Register 0x2158 (BB_OFFSET): A=00000001 B=00000005 (gem_ctx_isolation:1166) CRITICAL: Test assertion failure function compare_regs, file ../tests/i915/gem_ctx_isolation.c:474: (gem_ctx_isolation:1166) CRITICAL: Failed assertion: num_errors == 0 (gem_ctx_isolation:1166) CRITICAL: 1 registers mistached between clean. Subtest rcs0-none failed. **** DEBUG **** (gem_ctx_isolation:1166) igt_debugfs-DEBUG: Opening debugfs directory '/sys/kernel/debug/dri/0' (gem_ctx_isolation:1166) drmtest-DEBUG: Test requirement passed: is_i915_device(fd) && has_known_intel_chipset(fd) (gem_ctx_isolation:1166) igt_debugfs-DEBUG: Opening debugfs directory '/sys/kernel/debug/dri/0' (gem_ctx_isolation:1166) ioctl_wrappers-DEBUG: Test requirement passed: dir >= 0 (gem_ctx_isolation:1166) ioctl_wrappers-DEBUG: Test requirement passed: err == 0 (gem_ctx_isolation:1166) ioctl_wrappers-DEBUG: Test requirement passed: gem_has_ring(fd, ring) (gem_ctx_isolation:1166) igt_dummyload-DEBUG: Test requirement passed: nengine (gem_ctx_isolation:1166) drmtest-DEBUG: Test requirement passed: is_i915_device(fd) && has_known_intel_chipset(fd) (gem_ctx_isolation:1166) igt_debugfs-DEBUG: Opening debugfs directory '/sys/kernel/debug/dri/0' (gem_ctx_isolation:1166) ioctl_wrappers-DEBUG: Test requirement passed: dir >= 0 (gem_ctx_isolation:1166) ioctl_wrappers-DEBUG: Test requirement passed: err == 0 (gem_ctx_isolation:1166) ioctl_wrappers-DEBUG: Test requirement passed: gem_has_ring(fd, ring) (gem_ctx_isolation:1166) igt_dummyload-DEBUG: Test requirement passed: nengine (gem_ctx_isolation:1166) WARNING: Register 0x2158 (BB_OFFSET): A=00000001 B=00000005 (gem_ctx_isolation:1166) CRITICAL: Test assertion failure function compare_regs, file ../tests/i915/gem_ctx_isolation.c:474: (gem_ctx_isolation:1166) CRITICAL: Failed assertion: num_errors == 0 (gem_ctx_isolation:1166) CRITICAL: 1 registers mistached between clean. (gem_ctx_isolation:1166) igt_core-INFO: Stack trace: (gem_ctx_isolation:1166) igt_core-INFO: #0 ../lib/igt_core.c:1472 __igt_fail_assert() (gem_ctx_isolation:1166) igt_core-INFO: #1 ../tests/i915/gem_ctx_isolation.c:475 compare_regs() (gem_ctx_isolation:1166) igt_core-INFO: #2 ../tests/i915/gem_ctx_isolation.c:669 preservation() (gem_ctx_isolation:1166) igt_core-INFO: #3 ../tests/i915/gem_ctx_isolation.c:725 __real_main687() (gem_ctx_isolation:1166) igt_core-INFO: #4 ../tests/i915/gem_ctx_isolation.c:687 main() (gem_ctx_isolation:1166) igt_core-INFO: #5 ../csu/libc-start.c:344 __libc_start_main() (gem_ctx_isolation:1166) igt_core-INFO: #6 [_start+0x2a] **** END **** Subtest rcs0-none: FAIL (0.220s)
commit 478452fece3997dfacaa4d6babe6b8bf6fef784f Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Mon Jan 7 12:35:27 2019 +0000 i915/gem_ctx_isolation: Ignore the low bits of BB_OFFSET On Skylake, BB_OFFSET seems to be unstable. Since this is an offset into the batch at the time of CS execution, it should be actively written to as we read from the register so allow it a qword of discrepancy (since the CS should be reading in qwords). This still allows us to detect dirt across the rest of the register field, should that be required. v2: restrict ignore_bits to only BIT(2) that we see fluctuate in testing (Antonio) Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Antonio Argenziano <antonio.argenziano@intel.com>
The CI Bug Log issue associated to this bug has been updated. ### New filters associated * BXT, SKL: igt@gem_ctx_isolation@rcs0-* - fail - Test assertion failure function compare_regs.*\n.*Failed assertion: num_errors == 0 - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_190/fi-apl-guc/igt@gem_ctx_isolation@rcs0-none.html - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_190/fi-skl-6700k2/igt@gem_ctx_isolation@rcs0-dirty-switch.html - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_190/fi-skl-iommu/igt@gem_ctx_isolation@rcs0-dirty-switch.html - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_181/fi-apl-guc/igt@gem_ctx_isolation@rcs0-none.html - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_181/fi-skl-6700k2/igt@gem_ctx_isolation@rcs0-dirty-switch.html - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_181/fi-skl-iommu/igt@gem_ctx_isolation@rcs0-dirty-switch.html - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_182/fi-apl-guc/igt@gem_ctx_isolation@rcs0-none.html - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_182/fi-skl-6700k2/igt@gem_ctx_isolation@rcs0-dirty-switch.html - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_182/fi-skl-iommu/igt@gem_ctx_isolation@rcs0-dirty-switch.html - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_183/fi-apl-guc/igt@gem_ctx_isolation@rcs0-none.html - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_183/fi-skl-6700k2/igt@gem_ctx_isolation@rcs0-dirty-switch.html - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_183/fi-skl-iommu/igt@gem_ctx_isolation@rcs0-dirty-switch.html - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_184/fi-apl-guc/igt@gem_ctx_isolation@rcs0-none.html - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_184/fi-skl-6700k2/igt@gem_ctx_isolation@rcs0-dirty-switch.html - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_184/fi-skl-iommu/igt@gem_ctx_isolation@rcs0-dirty-switch.html - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_185/fi-apl-guc/igt@gem_ctx_isolation@rcs0-none.html - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_185/fi-skl-6700k2/igt@gem_ctx_isolation@rcs0-dirty-switch.html - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_185/fi-skl-iommu/igt@gem_ctx_isolation@rcs0-dirty-switch.html - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_186/fi-skl-6700k2/igt@gem_ctx_isolation@rcs0-dirty-switch.html - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_186/fi-skl-iommu/igt@gem_ctx_isolation@rcs0-dirty-switch.html - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_187/fi-apl-guc/igt@gem_ctx_isolation@rcs0-none.html - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_187/fi-skl-6700k2/igt@gem_ctx_isolation@rcs0-dirty-switch.html - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_187/fi-skl-iommu/igt@gem_ctx_isolation@rcs0-dirty-switch.html - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_188/fi-apl-guc/igt@gem_ctx_isolation@rcs0-none.html - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_188/fi-skl-6700k2/igt@gem_ctx_isolation@rcs0-dirty-switch.html - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_188/fi-skl-iommu/igt@gem_ctx_isolation@rcs0-dirty-switch.html - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_189/fi-apl-guc/igt@gem_ctx_isolation@rcs0-none.html - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_189/fi-skl-6700k2/igt@gem_ctx_isolation@rcs0-dirty-switch.html
A CI Bug Log filter associated to this bug has been updated: {- BXT, SKL: igt@gem_ctx_isolation@rcs0-* - fail - Test assertion failure function compare_regs.*\n.*Failed assertion: num_errors == 0 -} {+ BXT, SKL CFL: igt@gem_ctx_isolation@rcs0-* - fail - Test assertion failure function compare_regs.*\n.*Failed assertion: num_errors == 0 +} New failures caught by the filter: * https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_215/fi-cfl-guc/igt@gem_ctx_isolation@rcs0-none.html
A CI Bug Log filter associated to this bug has been updated: {- BXT, SKL CFL: igt@gem_ctx_isolation@rcs0-* - fail - Test assertion failure function compare_regs.*\n.*Failed assertion: num_errors == 0 -} {+ BXT, SKL KBL CFL: igt@gem_ctx_isolation@rcs0-* - fail - Test assertion failure function compare_regs.*\n.*Failed assertion: num_errors == 0 +} No new failures caught with the new filter
(In reply to Chris Wilson from comment #1) > commit 478452fece3997dfacaa4d6babe6b8bf6fef784f > Author: Chris Wilson <chris@chris-wilson.co.uk> > Date: Mon Jan 7 12:35:27 2019 +0000 > > i915/gem_ctx_isolation: Ignore the low bits of BB_OFFSET > > On Skylake, BB_OFFSET seems to be unstable. Since this is an > offset into the batch at the time of CS execution, it should be actively > written to as we read from the register so allow it a qword of > discrepancy (since the CS should be reading in qwords). This still > allows us to detect dirt across the rest of the register field, should > that be required. > > v2: restrict ignore_bits to only BIT(2) that we see fluctuate in testing > (Antonio) > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > Reviewed-by: Antonio Argenziano <antonio.argenziano@intel.com> Seems like it is still not sufficient: - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_215/fi-cfl-guc/igt@gem_ctx_isolation@rcs0-none.html - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_236/fi-kbl-7560u/igt@gem_ctx_isolation@rcs0-none.html
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