Bug 110201 - [ivb] mesa 19.0.0 breaks rendering in kitty
Summary: [ivb] mesa 19.0.0 breaks rendering in kitty
Status: RESOLVED FIXED
Alias: None
Product: Mesa
Classification: Unclassified
Component: Drivers/DRI/i965 (show other bugs)
Version: 19.0
Hardware: Other All
: medium normal
Assignee: Ian Romanick
QA Contact: Intel 3D Bugs Mailing List
URL:
Whiteboard:
Keywords: bisected, regression
Depends on:
Blocks:
 
Reported: 2019-03-20 03:55 UTC by Kovid Goyal
Modified: 2019-04-17 07:31 UTC (History)
1 user (show)

See Also:
i915 platform:
i915 features:


Attachments
glxinfo output (31.06 KB, text/plain)
2019-03-20 03:55 UTC, Kovid Goyal
Details
api trace output of running kitty on mesa 19 (195.04 KB, application/x-sega-cd-rom)
2019-03-20 03:57 UTC, Kovid Goyal
Details

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Description Kovid Goyal 2019-03-20 03:55:57 UTC
Created attachment 143736 [details]
glxinfo output

Since upgrading to mesa 19.0.0 rendering in kitty (https://sw.kovidgoyal.net/kitty/) an OpenGL terminal is broken, with various artifacts, for details, see https://github.com/kovidgoyal/kitty/issues/1484

Downgrading mesa to 18.3.4 fixes it. I have a report from a user that mesa 18.3.5 also breaks it, but I cannot confirm myself. This is on Arch Linux x64 up-to-date.

I have attached output of glxinfo. 

To reproduce, simply install kitty and run it with mesa 19 -- under Wayland I get the first line in the terminal blinking with the cursor. Under X11 I get the first four characters being not rendered.

I have attached glxinfo and apitrace output running kitty with mesa 19.
Comment 1 Kovid Goyal 2019-03-20 03:57:02 UTC
Created attachment 143737 [details]
api trace output of running kitty on mesa 19
Comment 2 Denis 2019-03-20 12:34:04 UTC
hi, thanks for the report. I reproduced issue on my IVB machine in the app (and in your apitrace, thanks and for it).
Below bisected result:



test@test-HP-Z220-SFF-Workstation:~/mesa$ git bisect good
4cd1a0be76883c2b13aae8c97972e8f1404d06f7 is the first bad commit
commit 4cd1a0be76883c2b13aae8c97972e8f1404d06f7
Author: Ian Romanick <ian.d.romanick@intel.com>
Date:   Tue Jun 19 18:09:05 2018 -0700

    i965/vec4: Propagate conditional modifiers from more compares to other compares
    
    If there is a CMP.NZ that compares a single component (via a .zzzz
    swizzle, for example) with 0, it can propagate its conditional modifier
    back to a previous CMP that writes only that component.  The specific
    case that I saw was:
    
        cmp.l.f0(8)     g42<1>.xF       g61<4>.xF       (abs)g18<4>.zF
        ...
        cmp.nz.f0(8)    null<1>D        g42<4>.xD       0D
    
    In this case we can just delete the second CMP.
    
    No changes on Broadwell or Skylake because they do not use the vec4
    backend.  Also no changes on GM45 or Iron Lake.
    
    Sandy Bridge, Ivy Bridge, and Haswell had similar results. (Sandy Bridge shown)
    total instructions in shared programs: 10856676 -> 10852569 (-0.04%)
    instructions in affected programs: 228322 -> 224215 (-1.80%)
    helped: 1331
    HURT: 0
    helped stats (abs) min: 1 max: 7 x̄: 3.09 x̃: 4
    helped stats (rel) min: 0.11% max: 6.67% x̄: 1.88% x̃: 1.83%
    95% mean confidence interval for instructions value: -3.19 -2.99
    95% mean confidence interval for instructions %-change: -1.93% -1.83%
    Instructions are helped.
    
    total cycles in shared programs: 154788865 -> 154732047 (-0.04%)
    cycles in affected programs: 2485892 -> 2429074 (-2.29%)
    helped: 1097
    HURT: 59
    helped stats (abs) min: 2 max: 168 x̄: 51.96 x̃: 64
    helped stats (rel) min: 0.12% max: 12.70% x̄: 3.44% x̃: 2.22%
    HURT stats (abs)   min: 2 max: 16 x̄: 3.02 x̃: 2
    HURT stats (rel)   min: 0.18% max: 0.83% x̄: 0.64% x̃: 0.71%
    95% mean confidence interval for cycles value: -51.04 -47.26
    95% mean confidence interval for cycles %-change: -3.40% -3.07%
    Cycles are helped.
    
    Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
    Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

:040000 040000 999198c729d569626942c3cbf2be1c8568188704 aa5820d52e85e7bcb6948cb7049a90e62d73f1be M	src
Comment 3 Lionel Landwerlin 2019-03-20 12:37:43 UTC
(In reply to Denis from comment #2)
> hi, thanks for the report. I reproduced issue on my IVB machine in the app
> (and in your apitrace, thanks and for it).
> Below bisected result:
> 
> 
> 
> test@test-HP-Z220-SFF-Workstation:~/mesa$ git bisect good
> 4cd1a0be76883c2b13aae8c97972e8f1404d06f7 is the first bad commit
> commit 4cd1a0be76883c2b13aae8c97972e8f1404d06f7
> Author: Ian Romanick <ian.d.romanick@intel.com>
> Date:   Tue Jun 19 18:09:05 2018 -0700
> 
>     i965/vec4: Propagate conditional modifiers from more compares to other
> compares
>     
>     If there is a CMP.NZ that compares a single component (via a .zzzz
>     swizzle, for example) with 0, it can propagate its conditional modifier
>     back to a previous CMP that writes only that component.  The specific
>     case that I saw was:
>     
>         cmp.l.f0(8)     g42<1>.xF       g61<4>.xF       (abs)g18<4>.zF
>         ...
>         cmp.nz.f0(8)    null<1>D        g42<4>.xD       0D
>     
>     In this case we can just delete the second CMP.
>     
>     No changes on Broadwell or Skylake because they do not use the vec4
>     backend.  Also no changes on GM45 or Iron Lake.
>     
>     Sandy Bridge, Ivy Bridge, and Haswell had similar results. (Sandy Bridge
> shown)
>     total instructions in shared programs: 10856676 -> 10852569 (-0.04%)
>     instructions in affected programs: 228322 -> 224215 (-1.80%)
>     helped: 1331
>     HURT: 0
>     helped stats (abs) min: 1 max: 7 x̄: 3.09 x̃: 4
>     helped stats (rel) min: 0.11% max: 6.67% x̄: 1.88% x̃: 1.83%
>     95% mean confidence interval for instructions value: -3.19 -2.99
>     95% mean confidence interval for instructions %-change: -1.93% -1.83%
>     Instructions are helped.
>     
>     total cycles in shared programs: 154788865 -> 154732047 (-0.04%)
>     cycles in affected programs: 2485892 -> 2429074 (-2.29%)
>     helped: 1097
>     HURT: 59
>     helped stats (abs) min: 2 max: 168 x̄: 51.96 x̃: 64
>     helped stats (rel) min: 0.12% max: 12.70% x̄: 3.44% x̃: 2.22%
>     HURT stats (abs)   min: 2 max: 16 x̄: 3.02 x̃: 2
>     HURT stats (rel)   min: 0.18% max: 0.83% x̄: 0.64% x̃: 0.71%
>     95% mean confidence interval for cycles value: -51.04 -47.26
>     95% mean confidence interval for cycles %-change: -3.40% -3.07%
>     Cycles are helped.
>     
>     Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
>     Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> 
> :040000 040000 999198c729d569626942c3cbf2be1c8568188704
> aa5820d52e85e7bcb6948cb7049a90e62d73f1be M	src

Then it should be fixed by : 

commit 6e184147ddce11e90c269a47af7d7395f5ed9c12
Author: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Date:   Wed Feb 27 15:53:21 2019 +0000

    intel/compiler: use correct swizzle for replacement
    
    The optimization in 4cd1a0be76883c introduced a replacement of :
    
    cmp(8).z.f0.0 vgrf11.y:D, vgrf10.xxxx:D, vgrf2.xyyy:D
    ...
    cmp(8).nz.f0.0 null.x:D, vgrf11.yyyy:D, 0D
    
    By :
    
    cmp(8).z.f0.0 vgrf15.x:D, vgrf10.xxxx:D, vgrf2.yyyy:D
    ...
    mov(8) vgrf11.y:D, vgrf15.yyyy:D
    
    The first cmp instruction is storing in x while the second mov is
    sourcing from y. We need to take into account where the replacement on
    the scan_inst destination is going to store thing so that the
    replacement mov can source things from the correct location.
    
    Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
    Fixes: 4cd1a0be76883c ("i965/vec4: Propagate conditional modifiers from more compares to other compares")
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109759
    Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Comment 4 Denis 2019-03-20 12:45:16 UTC
that was the first I checked, Lionel.

OpenGL ES profile version string: OpenGL ES 3.0 Mesa 19.1.0-devel (git-4fa61273a8)

this latest master includes mentioned commit.
But on IVB kitty.trace (from the https://bugs.freedesktop.org/show_bug.cgi?id=109759) and apitrace from current issue issue is visible and reproducable
Comment 5 Denis 2019-03-20 12:58:42 UTC
also I re-checked HSW and SNB - they work fine with provided commit. Issue is only on IVB
Comment 6 Lionel Landwerlin 2019-03-20 16:22:50 UTC
(In reply to Denis from comment #5)
> also I re-checked HSW and SNB - they work fine with provided commit. Issue
> is only on IVB

Thanks Denis. That's odd, I can't really see what else is different for IVB...

Did you see the issue with 18.3.5 as well?
Comment 7 Denis 2019-03-20 17:14:51 UTC
>Did you see the issue with 18.3.5 as well?

I bisected between 18.2.8 (my system version) and master.
Just built 18.3.5 and issue doesn't reproduce in it.

I can ask our devs to debug mesa on IVB. Or, if you have suggestions or ideas to try - I am happy to check/support you.
Comment 8 Lionel Landwerlin 2019-03-20 17:21:24 UTC
(In reply to Denis from comment #7)
> >Did you see the issue with 18.3.5 as well?
> 
> I bisected between 18.2.8 (my system version) and master.
> Just built 18.3.5 and issue doesn't reproduce in it.
> 
> I can ask our devs to debug mesa on IVB. Or, if you have suggestions or
> ideas to try - I am happy to check/support you.

Not a lot of ideas unfortunately.
Usually I fallback to diff the debug traces or aub files.

One last test that would be helpful is whether 6e184147ddce11e90c269a47af7d7395f5ed9c12 fixed the issue on IVB and it got broken again later.
Comment 9 Denis 2019-03-20 17:31:19 UTC
>6e184147ddce11e90c269a47af7d7395f5ed9c12 fixed the issue on IVB and it got broken again later.

Mesa on this commit also reproduces this issue on IVB
Comment 10 Danylo 2019-03-22 15:41:05 UTC
I made a possible fix: https://gitlab.freedesktop.org/mesa/mesa/merge_requests/512
Comment 11 Sergii Romantsov 2019-03-25 17:24:14 UTC
Piglit-test:
https://gitlab.freedesktop.org/mesa/piglit/merge_requests/28
Comment 12 Sergii Romantsov 2019-04-17 07:31:50 UTC
Should be fixed by (https://gitlab.freedesktop.org/mesa/mesa/merge_requests/520):
commit 04508f57d1d36587f3cc048f0f5dae0611f9330c
Author: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Date:   Mon Mar 25 14:15:27 2019 +0200

    intel/compiler: Do not reswizzle dst if instruction writes to flag register


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