Bug 110259 - radv: Sampling depth-stencil image in GENERAL layout returns nothing but zero (regression, bisected)
Summary: radv: Sampling depth-stencil image in GENERAL layout returns nothing but zero...
Alias: None
Product: Mesa
Classification: Unclassified
Component: Drivers/Vulkan/radeon (show other bugs)
Version: git
Hardware: Other All
: medium normal
Assignee: mesa-dev
QA Contact: mesa-dev
Depends on:
Reported: 2019-03-27 12:11 UTC by Philip Rebohle
Modified: 2019-03-29 07:28 UTC (History)
0 users

See Also:
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i915 features:


Description Philip Rebohle 2019-03-27 12:11:55 UTC

in some cases, DXVK creates depth-stencil images that are never transitioned out of VK_IMAGE_LAYOUT_GENERAL. From a D3D11 point of view, these images are only ever used for data transfers, and some of those transfers are implemented via compute shaders, so the usage flags are (TRANSFER_SRC | TRANSFER_DST | SAMPLED).

The problem is that the compute shaders in question read nothing but zeroes when using the GENERAL layout for sampling. It does work correctly when using SHADER_READ_ONLY_OPTIMAL, and it also works fine when setting RADV_DEBUG=nohiz.

Here's a renderdoc capture illustrating the issue:

The bookmarked dispatch call reads the image and packs its contents into a buffer. All buffer values should be 0x00FFFFFF if things work correctly, but are 0x00000000 right now.

The commit which introduced the issue is:

    commit 3a2e93147f7fa4a6fd17313353113a33291c5ce0 (refs/bisect/bad)
    Author: Samuel Pitoiset <samuel.pitoiset@gmail.com>
    Date:   Thu Mar 14 14:27:03 2019 +0100

        radv: always initialize HTILE when the src layout is UNDEFINED

This issue currently breaks the games Lords of the Fallen and The Surge.

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