Bug 110593 - [CI][SHARDS] igt@i915_pm_sseu@full-enable - fail - Failed assertion: pos != NULL
Summary: [CI][SHARDS] igt@i915_pm_sseu@full-enable - fail - Failed assertion: pos != NULL
Status: RESOLVED DUPLICATE of bug 110584
Alias: None
Product: DRI
Classification: Unclassified
Component: DRM/Intel (show other bugs)
Version: DRI git
Hardware: Other All
: high normal
Assignee: Intel GFX Bugs mailing list
QA Contact: Intel GFX Bugs mailing list
URL:
Whiteboard: ReadyForDev
Keywords:
Depends on:
Blocks:
 
Reported: 2019-05-03 06:17 UTC by Lakshmi
Modified: 2019-07-24 08:40 UTC (History)
2 users (show)

See Also:
i915 platform: SKL
i915 features: power/Other


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Description Lakshmi 2019-05-03 06:17:58 UTC
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6024/shard-skl1/igt@i915_pm_sseu@full-enable.html

Starting subtest: full-enable
(i915_pm_sseu:2470) CRITICAL: Test assertion failure function dbg_get_int, file ../tests/i915/i915_pm_sseu.c:120:
(i915_pm_sseu:2470) CRITICAL: Failed assertion: pos != NULL
Subtest full-enable failed.
**** DEBUG ****
U: no
(i915_pm_sseu:2470) DEBUG:   Has Slice Power Gating: no
(i915_pm_sseu:2470) DEBUG:   Has Subslice Power Gating: no
(i915_pm_sseu:2470) DEBUG:   Has EU Power Gating: yes
(i915_pm_sseu:2470) DEBUG: SSEU Device Status
(i915_pm_sseu:2470) DEBUG:   Enabled Slice Mask: 0000
(i915_pm_sseu:2470) DEBUG:   Enabled Slice Total: 0
(i915_pm_sseu:2470) DEBUG:   Enabled Subslice Total: 0
(i915_pm_sseu:2470) DEBUG:   Enabled EU Total: 0
(i915_pm_sseu:2470) DEBUG:   Enabled EU Per Subslice: 0
(i915_pm_sseu:2470) CRITICAL: Test assertion failure function dbg_get_int, file ../tests/i915/i915_pm_sseu.c:120:
(i915_pm_sseu:2470) CRITICAL: Failed assertion: pos != NULL
(i915_pm_sseu:2470) igt_core-INFO: Stack trace:
(i915_pm_sseu:2470) igt_core-INFO:   #0 ../lib/igt_core.c:1476 __igt_fail_assert()
(i915_pm_sseu:2470) igt_core-INFO:   #1 ../tests/i915/i915_pm_sseu.c:121 dbg_get_int()
(i915_pm_sseu:2470) igt_core-INFO:   #2 ../tests/i915/i915_pm_sseu.c:204 dbg_get_status()
(i915_pm_sseu:2470) igt_core-INFO:   #3 ../tests/i915/i915_pm_sseu.c:372 full_enable()
(i915_pm_sseu:2470) igt_core-INFO:   #4 ../tests/i915/i915_pm_sseu.c:397 __real_main388()
(i915_pm_sseu:2470) igt_core-INFO:   #5 ../tests/i915/i915_pm_sseu.c:388 main()
(i915_pm_sseu:2470) igt_core-INFO:   #6 ../csu/libc-start.c:344 __libc_start_main()
(i915_pm_sseu:2470) igt_core-INFO:   #7 [_start+0x2a]
****  END  ****
Subtest full-enable: FAIL (0.122s)
Comment 1 Lakshmi 2019-05-03 06:30:16 UTC
@Lionel any help here, this bug is similar to Bug 105400 but occurring on SKL.
Comment 2 CI Bug Log 2019-05-03 06:31:22 UTC
The CI Bug Log issue associated to this bug has been updated.

### New filters associated

* SKL: igt@i915_pm_sseu@full-enable - fail - Failed assertion: pos != NULL
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6024/shard-skl1/igt@i915_pm_sseu@full-enable.html
Comment 3 Lionel Landwerlin 2019-05-03 08:53:11 UTC
I think there is another bug about this problem (can't remember the number).
I left a comment explaining why we should rewrite this test as an i915 self test.
Essentially reading the values of the powergating registers from the CPU is racy.
These register only contain values after the GPU has run at least a single context. This test fails because we've waken up uncore, but no context has been run on the RCS, leaving the EUs still not powered on (hence 0 values).
Comment 4 Arek Hiler 2019-07-24 08:40:14 UTC
This is actually an instance of https://bugs.freedesktop.org/show_bug.cgi?id=110584

The effect is the same - same machines affected and we are powergated when we expect not to be, but just a bit more than in the 110584. Because of that we don't even have "Enabled Slice0 subslices:" line in the debugfs.

With https://patchwork.freedesktop.org/series/64158/ the error message will change to something more meaningful, maybe even the same as in the other bug.

*** This bug has been marked as a duplicate of bug 110584 ***


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