Bug 111468 - [CI][SHARDS] igt@gem_set_tiling_vs_(pwrite|blt@untiled-to-tiled) - fail - Failed assertion: data[i] == i
Summary: [CI][SHARDS] igt@gem_set_tiling_vs_(pwrite|blt@untiled-to-tiled) - fail - Fai...
Status: RESOLVED FIXED
Alias: None
Product: DRI
Classification: Unclassified
Component: DRM/Intel (show other bugs)
Version: XOrg git
Hardware: Other All
: high not set
Assignee: Intel GFX Bugs mailing list
QA Contact: Intel GFX Bugs mailing list
URL:
Whiteboard:
Keywords:
Depends on:
Blocks:
 
Reported: 2019-08-23 06:59 UTC by Martin Peres
Modified: 2019-08-23 18:57 UTC (History)
1 user (show)

See Also:
i915 platform: BXT, GLK
i915 features: GEM/Other


Attachments

Description Martin Peres 2019-08-23 06:59:19 UTC
https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5148/shard-apl5/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html

Starting subtest: untiled-to-tiled
Test assertion failure function do_test, file ../tests/i915/gem_set_tiling_vs_blt.c:203:
(gem_set_tiling_vs_blt:9031) CRITICAL: Failed assertion: data[i] == i
Comment 1 CI Bug Log 2019-08-23 06:59:37 UTC
The CI Bug Log issue associated to this bug has been updated.

### New filters associated

* APL GLK: igt@gem_set_tiling_vs_(pwrite|blt@untiled-to-tiled) - fail - Failed assertion: data[i] == i
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_4841/shard-apl2/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_4841/shard-apl5/igt@gem_set_tiling_vs_pwrite.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_4841/shard-glk2/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_4841/shard-glk8/igt@gem_set_tiling_vs_pwrite.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14135/shard-apl6/igt@gem_set_tiling_vs_pwrite.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14135/shard-glk4/igt@gem_set_tiling_vs_pwrite.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14135/shard-glk8/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6764/shard-glk2/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5148/shard-apl5/igt@gem_set_tiling_vs_pwrite.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5148/shard-apl5/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5148/shard-glk4/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6765/shard-apl2/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6765/shard-glk2/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6765/shard-glk4/igt@gem_set_tiling_vs_pwrite.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14140/shard-apl4/igt@gem_set_tiling_vs_pwrite.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14140/shard-apl4/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14140/shard-glk2/igt@gem_set_tiling_vs_pwrite.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14140/shard-glk9/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_4833/shard-apl7/igt@gem_set_tiling_vs_pwrite.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_4833/shard-glk1/igt@gem_set_tiling_vs_pwrite.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_4836/shard-apl1/igt@gem_set_tiling_vs_pwrite.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_4836/shard-glk9/igt@gem_set_tiling_vs_pwrite.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_4838/shard-apl2/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_4838/shard-apl2/igt@gem_set_tiling_vs_pwrite.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_4838/shard-glk2/igt@gem_set_tiling_vs_pwrite.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_4838/shard-glk7/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14134/shard-apl7/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14134/shard-apl7/igt@gem_set_tiling_vs_pwrite.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14134/shard-glk4/igt@gem_set_tiling_vs_pwrite.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14134/shard-glk9/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
Comment 2 Chris Wilson 2019-08-23 08:15:51 UTC
An idea, https://patchwork.freedesktop.org/series/65645/
Comment 3 Chris Wilson 2019-08-23 18:57:03 UTC
commit 636e83f2f208555c3d19d8b454ebdd8d8f4652cc (HEAD -> drm-intel-next-queued, drm-intel/for-linux-next, drm-intel/drm-intel-next-queued)
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Fri Aug 23 16:39:44 2019 +0100

    drm/i915: Flush the existing fence before GGTT read/write
    
    Our fence management is lazy, very lazy. If the user marks an object as
    untiled, we do not immediately flush the fence but merely mark it as
    dirty. On the next use we have to remember to check and remove the fence,
    by which time we hope it is idle and we do not have to wait.
    
    v2: Throw away the old fence on the next ggtt_pin.
    
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111468
    Fixes: 1f7fd484fff1 ("drm/i915: Replace i915_vma_put_fence()")
    Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
    Cc: Matthew Auld <matthew.auld@intel.com>
    Reviewed-by: Matthew Auld <matthew.auld@intel.com>
    Link: https://patchwork.freedesktop.org/patch/msgid/20190823153944.20630-1-chris@chris-wilson.co.uk


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