Large enough workgroup sizes that cause the Intel compiler back-end to generate SIMD32 code are currently broken on master in combination with some shader features that cause the back-end to allocate VGRFs larger than 16 GRFs, which aren't supported by the register allocator and other back-end compiler passes, and lead to assertion failures like:
"shader_runner: ../src/intel/compiler/brw_fs.cpp:2020: void fs_visitor::split_virtual_grfs(): Assertion `offset <= MAX_VGRF_SIZE' failed.
Aborted (core dumped)"
I've written the following Piglit test that reproduces the issue:
I bisected the regressions to change:
Author: Jason Ekstrand <email@example.com>
Date: Wed May 29 17:46:55 2019 -0500
intel/fs: Add an UNDEF instruction to avoid excess live ranges
With 8 and 16-bit types and anything where we have to use non-trivial
strides registersto deal with restrictions, we end up with things that
look like partial writes even though we don't care about any values in
the register except those written by that instruction. This is
particularly important when dealing with loops because liveness sees
is_partial_write and the fact that an old version from a previous loop
iteration may be valid at that point and extends all purely partially
written values to the entire loop.
This commit adds a new UNDEF instruction which does nothing (the
generator doesn't emit anything) but which does a fake write to the
register. This informs liveness that we don't care about any values
before that point so it won't consider those registers to be falsely
live. We can safely emit UNDEF instructions for all SSA values that
come in from NIR and nearly all temporaries generated by various stages
of the compiler. In particular, we need to insert UNDEF instructions
when we handle region restrictions because the newly allocated registers
are almost guaranteed to be partially written.
No shader-db changes.
Reviewed-by: Matt Turner <firstname.lastname@example.org>"
I had a half-baked fix for this but it seems like Jason is in the mood of fixing SIMD32 regressions -- So here you got another one.
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