Bug 111600 - [CI][RESUME] igt@* - dmesg-warn / dmesg-fail - *ERROR* CPU pipe [ABC] FIFO underrun
Summary: [CI][RESUME] igt@* - dmesg-warn / dmesg-fail - *ERROR* CPU pipe [ABC] FIFO un...
Status: NEW
Alias: None
Product: DRI
Classification: Unclassified
Component: DRM/Intel (show other bugs)
Version: XOrg git
Hardware: Other All
: high not set
Assignee: Intel GFX Bugs mailing list
QA Contact: Intel GFX Bugs mailing list
URL:
Whiteboard:
Keywords:
Depends on:
Blocks:
 
Reported: 2019-09-09 08:43 UTC by Martin Peres
Modified: 2019-09-16 06:54 UTC (History)
1 user (show)

See Also:
i915 platform: TGL
i915 features: display/Other


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Description Martin Peres 2019-09-09 08:43:55 UTC
https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_364/fi-tgl-u/igt@kms_vblank@pipe-a-accuracy-idle.html

<3> [515.854610] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe A FIFO underrun
Comment 1 CI Bug Log 2019-09-09 08:44:28 UTC
The CI Bug Log issue associated to this bug has been updated.

### New filters associated

* TGL: all tests - dmesg-warn / dmesg-fail - *ERROR* CPU pipe [ABC] FIFO underrun
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  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_362/fi-tgl-u/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_363/fi-tgl-u/igt@kms_atomic_transition@plane-all-transition-nonblocking.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_363/fi-tgl-u/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc.html
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  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_364/fi-tgl-u/igt@gem_eio@in-flight-suspend.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_364/fi-tgl-u/igt@kms_flip_tiling@flip-changes-tiling.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_364/fi-tgl-u/igt@kms_lease@setcrtc_implicit_plane.html
Comment 2 Maarten Lankhorst 2019-09-09 12:09:43 UTC
First FIFO underrun I see is with 7 planes enabled?
Comment 3 CI Bug Log 2019-09-11 10:59:16 UTC
A CI Bug Log filter associated to this bug has been updated:

{- TGL: all tests - dmesg-warn / dmesg-fail - *ERROR* CPU pipe [ABC] FIFO underrun -}
{+ TGL: all tests - dmesg-warn / dmesg-fail - *ERROR* CPU pipe [ABCD] FIFO underrun +}


  No new failures caught with the new filter
Comment 4 Stanislav Lisovskiy 2019-09-16 06:54:40 UTC
I have looked and there seems to be no memory bandwidth check working for tgl, currently intel_max_data_rate function which is used for final comparation to accept/reject display configuration looks like this(with current drm-tip):

        if (IS_GEN(dev_priv, 11))
                /*
                 * FIXME with SAGV disabled maybe we can assume
                 * point 1 will always be used? Seems to match
                 * the behaviour observed in the wild.
                 */
                return min3(icl_max_bw(dev_priv, num_planes, 0),
                            icl_max_bw(dev_priv, num_planes, 1),
                            icl_max_bw(dev_priv, num_planes, 2));
        else
                return UINT_MAX;
There are other similar parts in intel_bw.c also. Once I modified those to query pcode and calculate bandwidth same way as for ICL, FIFO underruns disappeared. 

So my guess is that we are simply lacking bandwidth part here. Do we have any plans on enabling that bandwidth code for TGL?


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