Bug 111712 - [CI][RESUME] igt@gem_exec_schedule@preempt* - skip - Test requirement: gem_scheduler_has_preemption(fd), SKIP
Summary: [CI][RESUME] igt@gem_exec_schedule@preempt* - skip - Test requirement: gem_sc...
Status: RESOLVED NOTABUG
Alias: None
Product: DRI
Classification: Unclassified
Component: DRM/Intel (show other bugs)
Version: XOrg git
Hardware: Other All
: high not set
Assignee: Intel GFX Bugs mailing list
QA Contact: Intel GFX Bugs mailing list
URL:
Whiteboard:
Keywords:
Depends on:
Blocks:
 
Reported: 2019-09-17 08:11 UTC by Martin Peres
Modified: 2019-09-17 08:37 UTC (History)
1 user (show)

See Also:
i915 platform: TGL
i915 features: GEM/execlists


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Description Martin Peres 2019-09-17 08:11:26 UTC
https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@preemptive-hang-bsd2.html

Test requirement not met in function __real_main1667, file ../tests/i915/gem_exec_schedule.c:1747:
Test requirement: gem_scheduler_has_preemption(fd)
Subtest preemptive-hang-bsd2: SKIP
Comment 1 CI Bug Log 2019-09-17 08:11:58 UTC
The CI Bug Log issue associated to this bug has been updated.

### New filters associated

* TGL: igt@gem_exec_schedule@preempt* - skip - Test requirement: gem_scheduler_has_preemption(fd), SKIP
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_371/fi-tgl-u/igt@gem_exec_schedule@preempt-hang-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_371/fi-tgl-u/igt@gem_exec_schedule@preempt-queue-contexts-chain-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@preempt-blt.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@preempt-queue-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@preempt-queue-bsd1.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@preempt-contexts-blt.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@preemptive-hang-vebox.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@preempt-contexts-bsd1.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@preempt-self-bsd1.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@preemptive-hang-bsd2.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@preempt-bsd2.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@preempt-queue-contexts-vebox.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd2.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@pi-ringfull-vebox.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@preempt-contexts-vebox.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@preempt-queue-blt.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@pi-ringfull-bsd2.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd1.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@preempt-other-chain-bsd1.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@preempt-bsd1.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@preempt-queue-chain-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@preempt-hang-bsd2.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@preempt-queue-contexts-chain-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@preempt-hang-bsd1.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@preempt-contexts-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@preemptive-hang-bsd1.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@preempt-queue-chain-vebox.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@preempt-queue-contexts-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@preempt-other-chain-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@preempt-queue-vebox.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@preempt-hang-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@preempt-contexts-bsd2.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@preempt-self-bsd2.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@pi-ringfull-blt.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@preempt-other-chain-blt.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@preempt-other-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@preempt-hang-vebox.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@preempt-other-vebox.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@preempt-vebox.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@preempt-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u2/igt@gem_exec_schedule@preempt-other-bsd2.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u2/igt@gem_exec_schedule@preempt-queue-chain-bsd2.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u2/igt@gem_exec_schedule@preempt-contexts-bsd1.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u2/igt@gem_exec_schedule@preemptive-hang-bsd2.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u2/igt@gem_exec_schedule@preempt-bsd2.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u2/igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd2.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u2/igt@gem_exec_schedule@pi-ringfull-vebox.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u2/igt@gem_exec_schedule@preempt-queue-blt.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u2/igt@gem_exec_schedule@pi-ringfull-bsd2.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u2/igt@gem_exec_schedule@preempt-other-chain-bsd1.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u2/igt@gem_exec_schedule@preempt-queue-contexts-chain-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u2/igt@gem_exec_schedule@preempt-self-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u2/igt@gem_exec_schedule@pi-ringfull-bsd1.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u2/igt@gem_exec_schedule@preempt-hang-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u2/igt@gem_exec_schedule@preempt-contexts-bsd2.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u2/igt@gem_exec_schedule@preempt-self-bsd2.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u2/igt@gem_exec_schedule@pi-ringfull-blt.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u2/igt@gem_exec_schedule@preempt-self-blt.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u2/igt@gem_exec_schedule@preempt-hang-vebox.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_369/fi-tgl-u/igt@gem_exec_schedule@preempt-queue-contexts-chain-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_369/fi-tgl-u/igt@gem_exec_schedule@preempt-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_369/fi-tgl-u/igt@gem_exec_schedule@preempt-queue-contexts-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_369/fi-tgl-u/igt@gem_exec_schedule@preemptive-hang-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_369/fi-tgl-u/igt@gem_exec_schedule@preempt-queue-chain-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_369/fi-tgl-u/igt@gem_exec_schedule@preempt-self-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_369/fi-tgl-u/igt@gem_exec_schedule@preempt-hang-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_369/fi-tgl-u/igt@gem_exec_schedule@preempt-other-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_369/fi-tgl-u/igt@gem_exec_schedule@pi-ringfull-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_369/fi-tgl-u/igt@gem_exec_schedule@preempt-queue-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_369/fi-tgl-u2/igt@gem_exec_schedule@preempt-queue-contexts-chain-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_369/fi-tgl-u2/igt@gem_exec_schedule@preempt-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_369/fi-tgl-u2/igt@gem_exec_schedule@preempt-queue-contexts-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_369/fi-tgl-u2/igt@gem_exec_schedule@preemptive-hang-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_369/fi-tgl-u2/igt@gem_exec_schedule@preempt-queue-chain-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_369/fi-tgl-u2/igt@gem_exec_schedule@preempt-self-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_369/fi-tgl-u2/igt@gem_exec_schedule@preempt-hang-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_369/fi-tgl-u2/igt@gem_exec_schedule@preempt-contexts-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_369/fi-tgl-u2/igt@gem_exec_schedule@preempt-other-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_369/fi-tgl-u2/igt@gem_exec_schedule@pi-ringfull-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_369/fi-tgl-u2/igt@gem_exec_schedule@preempt-other-chain-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_369/fi-tgl-u2/igt@gem_exec_schedule@preempt-queue-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_371/fi-tgl-u/igt@gem_exec_schedule@preempt-queue-chain-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_371/fi-tgl-u/igt@gem_exec_schedule@preempt-contexts-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_370/fi-tgl-u/igt@gem_exec_schedule@preempt-queue-contexts-chain-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_370/fi-tgl-u/igt@gem_exec_schedule@preempt-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_370/fi-tgl-u/igt@gem_exec_schedule@preempt-queue-contexts-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_370/fi-tgl-u/igt@gem_exec_schedule@preemptive-hang-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_370/fi-tgl-u/igt@gem_exec_schedule@preempt-queue-chain-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_370/fi-tgl-u/igt@gem_exec_schedule@preempt-self-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_370/fi-tgl-u/igt@gem_exec_schedule@preempt-hang-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_370/fi-tgl-u/igt@gem_exec_schedule@preempt-other-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_370/fi-tgl-u/igt@gem_exec_schedule@pi-ringfull-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_370/fi-tgl-u/igt@gem_exec_schedule@preempt-queue-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_370/fi-tgl-u2/igt@gem_exec_schedule@preempt-queue-contexts-chain-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_370/fi-tgl-u2/igt@gem_exec_schedule@preempt-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_370/fi-tgl-u2/igt@gem_exec_schedule@preempt-queue-contexts-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_370/fi-tgl-u2/igt@gem_exec_schedule@preemptive-hang-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_370/fi-tgl-u2/igt@gem_exec_schedule@preempt-self-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_370/fi-tgl-u2/igt@gem_exec_schedule@preempt-hang-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_370/fi-tgl-u2/igt@gem_exec_schedule@preempt-contexts-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_370/fi-tgl-u2/igt@gem_exec_schedule@preempt-other-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_370/fi-tgl-u2/igt@gem_exec_schedule@pi-ringfull-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_370/fi-tgl-u2/igt@gem_exec_schedule@preempt-queue-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_371/fi-tgl-u/igt@gem_exec_schedule@preempt-queue-contexts-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_371/fi-tgl-u/igt@gem_exec_schedule@preempt-other-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_371/fi-tgl-u/igt@gem_exec_schedule@preempt-other-chain-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_371/fi-tgl-u/igt@gem_exec_schedule@pi-ringfull-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_371/fi-tgl-u/igt@gem_exec_schedule@preempt-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_371/fi-tgl-u/igt@gem_exec_schedule@preemptive-hang-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_371/fi-tgl-u2/igt@gem_exec_schedule@preempt-queue-contexts-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_371/fi-tgl-u2/igt@gem_exec_schedule@preempt-other-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_371/fi-tgl-u2/igt@gem_exec_schedule@preempt-other-chain-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_371/fi-tgl-u2/igt@gem_exec_schedule@preempt-hang-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_371/fi-tgl-u2/igt@gem_exec_schedule@preempt-queue-contexts-chain-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_371/fi-tgl-u2/igt@gem_exec_schedule@preempt-queue-chain-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_371/fi-tgl-u2/igt@gem_exec_schedule@preempt-contexts-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_371/fi-tgl-u2/igt@gem_exec_schedule@pi-ringfull-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_371/fi-tgl-u2/igt@gem_exec_schedule@preempt-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_371/fi-tgl-u2/igt@gem_exec_schedule@preemptive-hang-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_371/fi-tgl-u2/igt@gem_exec_schedule@preempt-self-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_371/fi-tgl-u2/igt@gem_exec_schedule@preempt-queue-render.html
Comment 2 Martin Peres 2019-09-17 08:14:56 UTC
Probably caused by https://cgit.freedesktop.org/drm-tip/commit/?id=ee73e2795b416b829f0e00e7c43154922dff495b

author	Chris Wilson <chris@chris-wilson.co.uk>	2019-09-12 14:23:13 +0100
committer	Chris Wilson <chris@chris-wilson.co.uk>	2019-09-12 20:45:23 +0100
commit	ee73e2795b416b829f0e00e7c43154922dff495b

drm/i915/tgl: Disable preemption while being debugged
We see failures where the context continues executing past a
preemption event, eventually leading to situations where a request has
executed before we have event submitted it to HW! It seems like tgl is
ignoring our RING_TAIL updates, but more likely is that there is a
missing update required for our semaphore waits around preemption.

v2: And disable internal semaphore usage

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190912132313.12751-1-chris@chris-wilson.co.uk
Comment 3 Chris Wilson 2019-09-17 08:16:01 UTC
Both preemption and those engines are disabled due to incomplete implementations.
Comment 4 Martin Peres 2019-09-17 08:18:36 UTC
(In reply to Chris Wilson from comment #3)
> Both preemption and those engines are disabled due to incomplete
> implementations.

NOTABUG is for things that are expected and need to fixing (a test requiring a feature that is gone for example). We plan on making use of preemption, I am re-opening the bug to keep track of the issue.
Comment 5 Chris Wilson 2019-09-17 08:36:36 UTC
The tests are skipping exactly as intended as they have *nothing* to test.
Comment 6 CI Bug Log 2019-09-17 08:37:20 UTC
The CI Bug Log issue associated to this bug has been updated.

### New filters associated

* TGL: igt@gem_exec_balancer@semaphore(-resolve)? - skip - Test requirement: gem_scheduler_has_preemption(i915), SKIP
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_368/fi-tgl-u/igt@gem_exec_schedule@semaphore-resolve.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_369/fi-tgl-u/igt@gem_exec_schedule@semaphore-resolve.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_369/fi-tgl-u2/igt@gem_exec_balancer@semaphore.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_369/fi-tgl-u2/igt@gem_exec_schedule@semaphore-resolve.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_371/fi-tgl-u/igt@gem_exec_schedule@semaphore-resolve.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_370/fi-tgl-u/igt@gem_exec_balancer@semaphore.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_370/fi-tgl-u/igt@gem_exec_schedule@semaphore-resolve.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_370/fi-tgl-u2/igt@gem_exec_balancer@semaphore.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_370/fi-tgl-u2/igt@gem_exec_schedule@semaphore-resolve.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_371/fi-tgl-u/igt@gem_exec_balancer@semaphore.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_371/fi-tgl-u2/igt@gem_exec_schedule@semaphore-resolve.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_371/fi-tgl-u2/igt@gem_exec_balancer@semaphore.html


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