Bug 111938 - [CI][SHARDS] igt@kms_flip@.*-wf_vblank - fail - Failed assertion: fabs((elapsed - expected) / expected) <= 0.005
Summary: [CI][SHARDS] igt@kms_flip@.*-wf_vblank - fail - Failed assertion: fabs((elaps...
Status: NEW
Alias: None
Product: DRI
Classification: Unclassified
Component: DRM/Intel (show other bugs)
Version: DRI git
Hardware: Other All
: medium normal
Assignee: Intel GFX Bugs mailing list
QA Contact: Intel GFX Bugs mailing list
URL:
Whiteboard:
Keywords:
Depends on:
Blocks:
 
Reported: 2019-10-09 14:28 UTC by Lakshmi
Modified: 2019-10-10 16:25 UTC (History)
1 user (show)

See Also:
i915 platform: TGL
i915 features: display/Other


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Description Lakshmi 2019-10-09 14:28:24 UTC
https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5218/shard-tglb2/igt@kms_flip@flip-vs-absolute-wf_vblank.html
	
Starting subtest: flip-vs-absolute-wf_vblank
(kms_flip:1228) CRITICAL: Test assertion failure function check_state, file ../tests/kms_flip.c:531:
(kms_flip:1228) CRITICAL: Failed assertion: fabs((elapsed - expected) / expected) <= 0.005
(kms_flip:1228) CRITICAL: inconsistent vblank ts/seq: last 186.503342/4818, current 186.616776/4828: elapsed=113433.0us expected=110935.0us
Subtest flip-vs-absolute-wf_vblank failed.
Comment 1 CI Bug Log 2019-10-09 14:28:59 UTC
The CI Bug Log issue associated to this bug has been updated.

### New filters associated

* TGL: igt@kms_flip@.*-wf_vblank - fail - Failed assertion: fabs((elapsed - expected) / expected) &lt;= 0.005
  - https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3552/shard-tglb7/igt@kms_flip@flip-vs-blocking-wf-vblank.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5217/shard-tglb1/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14703/shard-tglb1/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5218/shard-tglb2/igt@kms_flip@flip-vs-absolute-wf_vblank.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7034/shard-tglb5/igt@kms_flip@flip-vs-absolute-wf_vblank.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7034/shard-tglb6/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3553/shard-tglb6/igt@kms_flip@flip-vs-blocking-wf-vblank.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7035/shard-tglb1/igt@kms_flip@flip-vs-absolute-wf_vblank.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7032/re-tgl-u/igt@kms_flip@flip-vs-absolute-wf_vblank.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7032/re-tgl-u/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7032/re-tgl-u/igt@kms_flip@flip-vs-blocking-wf-vblank.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14706/shard-tglb1/igt@kms_flip@flip-vs-absolute-wf_vblank.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_5132/shard-tglb6/igt@kms_flip@flip-vs-blocking-wf-vblank.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14711/shard-tglb4/igt@kms_flip@flip-vs-absolute-wf_vblank.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7037/shard-tglb1/igt@kms_flip@flip-vs-absolute-wf_vblank.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7037/shard-tglb6/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14712/shard-tglb3/igt@kms_flip@flip-vs-blocking-wf-vblank.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14716/shard-tglb5/igt@kms_flip@flip-vs-blocking-wf-vblank.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7039/shard-tglb3/igt@kms_flip@flip-vs-absolute-wf_vblank.html
Comment 2 Caz.Yokoyama 2019-10-10 16:25:02 UTC
Expectation maybe too strict from the facts
- On TGL
- 14 / 25 runs (56.0%) of failure rate
- elapsed=113433.0us expected=110935.0us


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