After applying the panel fitting patch (now in master), dithering in 24bpp modes breaks on my 945GM - color gradients are no longer smooth. In 16bpp this doesn't occur. The hardware: 00:02.0 VGA compatible controller [0300]: Intel Corporation Mobile 945GM/GMS, 943/940GML Express Integrated Graphics Controller [8086:27a2] (rev 03) 00:02.1 Display controller [0380]: Intel Corporation Mobile 945GM/GMS/GME, 943/940GML Express Integrated Graphics Controller [8086:27a6] (rev 03) Toshiba Satellite M105-S3074, 1280x800 panel.
Disabling PANEL_8TO6_DITHER_ENABLE doesn't help here.
Can you get register dumps from the working & broken drivers? I must be clobbering the LVDS register somehow, but I don't see where...
Here's a diff between the dumps: --- regdump_no_pfit.txt 2008-04-02 05:25:01.000000000 +0200 +++ regdump_pfit.txt 2008-04-02 05:25:01.000000000 +0200 @@ -19 +19 @@ -(II): LVDS: 0xc0308300 (enabled, pipe B, 18 bit, 1 channel) +(II): LVDS: 0xc0300300 (enabled, pipe B, 18 bit, 1 channel) @@ -28 +28 @@ -(II): PFIT_CONTROL: 0x00000008 +(II): PFIT_CONTROL: 0x00000000 @@ -41 +41 @@ -(II): PIPEASTAT: 0x80020203 (status: FIFO_UNDERRUN VBLANK_INT_ENABLE VSYNC_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS) +(II): PIPEASTAT: 0x80000203 (status: FIFO_UNDERRUN VSYNC_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS) @@ -71 +71 @@ -(II): PIPEBSTAT: 0x00020202 (status: VBLANK_INT_ENABLE VSYNC_INT_STATUS VBLANK_INT_STATUS) +(II): PIPEBSTAT: 0x00000242 (status: VSYNC_INT_STATUS LBLC_EVENT_STATUS VBLANK_INT_STATUS)
Hm, maybe things are reversed? --- regdump_no_pfit.txt 2008-04-02 05:25:01.000000000 +0200 +++ regdump_pfit.txt 2008-04-02 05:25:01.000000000 +0200 -(II): LVDS: 0xc0308300 (enabled, pipe B, 18 bit, 1 channel) +(II): LVDS: 0xc0300300 (enabled, pipe B, 18 bit, 1 channel) -(II): PFIT_CONTROL: 0x00000008 +(II): PFIT_CONTROL: 0x00000000 According to your diff, the "no pfit" tree sets the border bit and the dithering bit, maybe the diff is reversed? If so, this might help since it reverts the dither bit to the old behavior. diff --git a/src/i830_lvds.c b/src/i830_lvds.c index 33b4f26..ea0bcdb 100644 --- a/src/i830_lvds.c +++ b/src/i830_lvds.c @@ -542,23 +542,22 @@ i830_lvds_mode_fixup(xf86OutputPtr output, DisplayModePtr adjusted_mode->Clock = dev_priv->panel_fixed_mode->Clock; xf86SetModeCrtc(adjusted_mode, INTERLACE_HALVE_V); + /* Make sure pre-965s set dither correctly */ + if (!IS_I965G(pI830) && dev_priv->panel_wants_dither) + pfit_control |= PANEL_8TO6_DITHER_ENABLE; + /* Native modes don't need fitting */ if (adjusted_mode->HDisplay == mode->HDisplay && adjusted_mode->VDisplay == mode->VDisplay) { - pfit_control = 0; pfit_pgm_ratios = 0; border = 0; goto out; } - /* Basic panel fitting options */ - if (!IS_I965G(pI830)) { - if (dev_priv->panel_wants_dither) - pfit_control |= PANEL_8TO6_DITHER_ENABLE; - } else { + /* 965+ wants fuzzy fitting */ + if (IS_I965G(pI830)) pfit_control |= (intel_crtc->pipe << PFIT_PIPE_SHIFT) | PFIT_FILTER_FUZZY; - } /* * Deal with panel fitting options. Figure out how to stretch the image
(In reply to comment #4) > Hm, maybe things are reversed? > > --- regdump_no_pfit.txt 2008-04-02 05:25:01.000000000 +0200 > +++ regdump_pfit.txt 2008-04-02 05:25:01.000000000 +0200 > -(II): LVDS: 0xc0308300 (enabled, pipe B, 18 bit, 1 channel) > +(II): LVDS: 0xc0300300 (enabled, pipe B, 18 bit, 1 channel) > -(II): PFIT_CONTROL: 0x00000008 > +(II): PFIT_CONTROL: 0x00000000 > > According to your diff, the "no pfit" tree sets the border bit and the > dithering bit, maybe the diff is reversed? Both dumps were taken at 1280x800 native mode. I checked it once again and it really looks like the old code sets the border bit even then... > If so, this might help since it reverts the dither bit to the old behavior. > [...] It helps, the dithering bit is now set. Thank you!
Fix is in 15313, which Zhenyu will push shortly. *** This bug has been marked as a duplicate of bug 15313 ***
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