Bug 27667 - [945 bisected] Resume with VGA only causes flicker
Summary: [945 bisected] Resume with VGA only causes flicker
Status: CLOSED FIXED
Alias: None
Product: DRI
Classification: Unclassified
Component: DRM/Intel (show other bugs)
Version: unspecified
Hardware: x86 (IA32) Linux (All)
: medium normal
Assignee: Li Peng
QA Contact:
URL:
Whiteboard:
Keywords:
Depends on:
Blocks:
 
Reported: 2010-04-15 10:58 UTC by Alexander Lam
Modified: 2017-07-24 23:08 UTC (History)
2 users (show)

See Also:
i915 platform:
i915 features:


Attachments
dmesg with drm.debug=0x06 on kernel 2.6.34-rc3 (276.27 KB, text/plain)
2010-04-15 10:59 UTC, Alexander Lam
no flags Details
Xorg.log on kernel 2.6.34-rc3 (29.56 KB, text/plain)
2010-04-15 11:00 UTC, Alexander Lam
no flags Details
test.patch (1.10 KB, patch)
2010-05-18 20:40 UTC, Li Peng
no flags Details | Splinter Review

Description Alexander Lam 2010-04-15 10:58:28 UTC
I upgraded from 2.6.33.2 to 2.6.34-rc3 and came across issue:

I run my notebook with the VGA output on and the LVDS output off. In this configuration, after resume from disk or ram, the VGA monitor will show gray when the computer is idle. The actual desktop will show if I move the mouse or if the computer is busy. If I VT switch, tty's flicker too, but black. (Text shows if I type, if I stop, it won't be there).
Back In X with xrandr, If I switch the LVDS on at the same time, it goes away. Also, if I switch the LVDS on, turn VGA off, turn VGA on again, then turn LVDS off, all is okay too. All this is 100% reproducible.

Anholt asked me to bisect, I got this:
ee980b8003a25fbfed50c3367f2b426c870eaf90 is the first bad commit
commit ee980b8003a25fbfed50c3367f2b426c870eaf90
Author: Li Peng <peng.li@linux.intel.com>
Date:   Wed Jan 27 19:01:11 2010 +0800

    drm/i915: enable memory self refresh on 9xx

    Enabling memory self refresh (SR) on 9xx needs to set additional
    register bits. On 945, we need bit 31 of FW_BLC_SELF to enable the
    write to self refresh bit and bit 16 to enable the write of self
    refresh watermark. On 915, bit 12 of INSTPM is used to enable SR.

    SR will take effect when CPU enters C3+ state and its entry/exit
    should be automatically controlled by H/W, driver only needs to set
    SR enable bits in wm update. But this isn't safe in my test on 945
    because GPU is hung. So this patch explicitly enables SR when GPU
    is idle, and disables SR when it is busy. In my test on a netbook of
    945GSE chipset, it saves about 0.8W idle power.

    Signed-off-by: Li Peng <peng.li@intel.com>
    [anholt: rebased against 33c5fd121eabbccc9103daf6cda36941eb3c349f
    by adding disable of INSTPM SR bit on 915GM for two pipe setup]
    Signed-off-by: Eric Anholt <eric@anholt.net>
Comment 1 Alexander Lam 2010-04-15 10:59:18 UTC
Created attachment 35068 [details]
dmesg with drm.debug=0x06 on kernel 2.6.34-rc3

Notice pipe A underrun warnings after resume
Comment 2 Alexander Lam 2010-04-15 11:00:05 UTC
Created attachment 35069 [details]
Xorg.log on kernel 2.6.34-rc3
Comment 3 Li Peng 2010-05-18 20:40:45 UTC
Created attachment 35745 [details] [review]
test.patch

Could you help testing this patch and see if it resolve your problem ?
Comment 4 Alexander Lam 2010-05-20 16:38:35 UTC
(In reply to comment #3)
> Created an attachment (id=35745) [details]
> test.patch
> 
> Could you help testing this patch and see if it resolve your problem ?

Hi,
This patch appears to fix the problem. Thank you
Comment 5 Chris Wilson 2010-07-15 03:52:12 UTC
The patch is now upstream:

commit 45ac22c81b1088f5ac08dc5367f78c192d68d756
Author: Li Peng <peng.li@linux.intel.com>
Date:   Sat Jun 12 23:38:35 2010 +0800

    drm/i915: Turn on 945 self-refresh only if single CRTC is active
    
    Enable self-refresh on 945 when just one CRTC is activated.
    Otherwise user would get display flicker with dual display.
    
    This fixes https://bugs.freedesktop.org/show_bug.cgi?id=27667
    
    Signed-off-by: Li Peng <peng.li@intel.com>
    Reviewed-by: Adam Jackson <ajax@redhat.com>
    Signed-off-by: Eric Anholt <eric@anholt.net>


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