Bug 28624 - [r300g] too many texture indirections (was: fails to compile some fragment programs of Enemy Territory: Quake Wars)
Summary: [r300g] too many texture indirections (was: fails to compile some fragment pr...
Status: RESOLVED FIXED
Alias: None
Product: Mesa
Classification: Unclassified
Component: Drivers/DRI/r300 (show other bugs)
Version: git
Hardware: x86 (IA32) Linux (All)
: medium normal
Assignee: Default DRI bug account
QA Contact:
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Depends on:
Blocks:
 
Reported: 2010-06-20 06:44 UTC by almos
Modified: 2010-07-09 12:00 UTC (History)
0 users

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i915 platform:
i915 features:

Attachments
stderr with RADEON_DEBUG=fp (700.47 KB, text/plain)
2010-06-20 06:44 UTC, almos 		Details
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Description almos 2010-06-20 06:44:50 UTC 
Created attachment 36379 [details]
stderr with RADEON_DEBUG=fp

The driver prints the following:

r300compiler error: r300_fragprog_emit.c::begin_tex(): Too many texture indirections
r300 FP: Compiler Error:
r300_fragprog_emit.c::begin_tex(): Too many texture indirections
Using a dummy shader instead.

The attached log is done with RADEON_DEBUG=fp. It is stderr only, because et:qw fails to start (stops at 'loading UI') if stdout is redirected as well.
Comment 1 almos 2010-06-20 10:31:20 UTC 
my gpu is an rv350 (radeon 9600xt)
Comment 2 Marek Olšák 2010-07-05 09:26:36 UTC 
The failing shader:

FRAG
DCL IN[0], GENERIC[0], PERSPECTIVE
DCL IN[1], GENERIC[1], PERSPECTIVE
DCL IN[2], GENERIC[2], PERSPECTIVE
DCL IN[3], GENERIC[3], PERSPECTIVE
DCL IN[4], GENERIC[4], PERSPECTIVE
DCL IN[5], GENERIC[5], PERSPECTIVE
DCL IN[6], GENERIC[6], PERSPECTIVE
DCL IN[7], GENERIC[7], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL TEMP[0..1]
IMM FLT32 {    0.0714,     0.1071,     0.1429,     0.1786}
  0: TEX TEMP[0], IN[1], SAMP[0], RECT
  1: MUL TEMP[1], TEMP[0], IMM[0].yyyy
  2: TEX TEMP[0], IN[0], SAMP[0], RECT
  3: MAD TEMP[1], TEMP[0], IMM[0].xxxx, TEMP[1]
  4: TEX TEMP[0], IN[2], SAMP[0], RECT
  5: MAD TEMP[1], TEMP[0], IMM[0].zzzz, TEMP[1]
  6: TEX TEMP[0], IN[3], SAMP[0], RECT
  7: MAD TEMP[1], TEMP[0], IMM[0].wwww, TEMP[1]
  8: TEX TEMP[0], IN[4], SAMP[0], RECT
  9: MAD TEMP[1], TEMP[0], IMM[0].wwww, TEMP[1]
 10: TEX TEMP[0], IN[5], SAMP[0], RECT
 11: MAD TEMP[1], TEMP[0], IMM[0].zzzz, TEMP[1]
 12: TEX TEMP[0], IN[6], SAMP[0], RECT
 13: MAD TEMP[1], TEMP[0], IMM[0].yyyy, TEMP[1]
 14: TEX TEMP[0], IN[7], SAMP[0], RECT
 15: MAD OUT[0], TEMP[0], IMM[0].xxxx, TEMP[1]
 16: END

If we reorder all the instructions, rename a few registers etc. we will end up with 1 TEX block. This seems to be the third TEX scheduling bug in the compiler we know about.
Comment 3 Tom Stellard 2010-07-08 22:05:13 UTC 
This should be fixed by commit 8a8e311d8c3c60982d101826a4aa013672730e6c.  Can you try again with the latest git code?
Comment 4 almos 2010-07-09 11:53:12 UTC 
Fix confirmed. It doesn't print error messages, and the trees are not black anymore.
Comment 5 Marek Olšák 2010-07-09 12:00:53 UTC 
OK, closing..

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