Sparse spotted the following and it does look like the wrong order of cast and shift:
drivers/gpu/drm/radeon/evergreen.c:1140:78: warning: right shift by bigger than source value
efuse_box_bit_127_124 = (u8)(efuse_straps_3 & 0xF0000000) >> 28;
I think I agree with it that in that the value is truncated to u8 before being
shifted down by 28 and therefore always being 0. So easiest fix I guess is:
efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >>28);
Not sure what the effect of this would be, it seems to be in some very device specific code.
good catch. I've sent Dave a patch: