Bug 36648 - [bisected SNB]piglit fbo/fbo-alphatest-nocolor failed
[bisected SNB]piglit fbo/fbo-alphatest-nocolor failed
Product: Mesa
Classification: Unclassified
Component: Drivers/DRI/i965
All Linux (All)
: high major
Assigned To: Eric Anholt
Depends on:
  Show dependency treegraph
Reported: 2011-04-27 23:33 UTC by fangxun
Modified: 2011-05-19 20:56 UTC (History)
1 user (show)

See Also:
i915 platform:
i915 features:


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Description fangxun 2011-04-27 23:33:28 UTC
System Environment:
Arch:           x86_64
Platform:     Sandybridge  
Libdrm:  (master)2.4.25
Mesa:    (master)b8de75d53760fb359d10d6f4794f28097210cef4
Kernel: (drm-intel-next)daab1470018f025e0b1c8731dfb825ff421ffd9b

Bug detailed description:
This case failed on all our Sandybridge machines. Below is test output. 
Probe at (20,0)
  Expected: 1.000000 1.000000 1.000000 1.000000
  Observed: 0.000000 0.000000 0.000000 0.000000
PIGLIT: {'result': 'fail' }

Bisect shows 3b20f999bb7e9056e83ca09a842a9747d4ac1674 is the first bad commit.
commit 3b20f999bb7e9056e83ca09a842a9747d4ac1674
Author:     Eric Anholt <eric@anholt.net>
AuthorDate: Wed Mar 23 12:50:53 2011 -0700
Commit:     Eric Anholt <eric@anholt.net>
CommitDate: Tue Apr 26 12:20:05 2011 -0700

    i965/fs: Add support for 16-wide dispatch with uniforms in use.

    This is glued in in a bit of an ugly way -- we rely on the uniforms
    having been set up by 8-wide dispatch, and we just reuse them without
    the ability to add new uniforms for any reason, since the 8-wide
    compile is already completed.  Today, this all works out because our
    optimization passes are effectively the same for both and even if they
    weren't, we don't reduce the set of uniforms pushed after

    Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

Reproduce steps:
1. start X
2. ./fbo-alphatest-nocolor -auto
Comment 1 Eric Anholt 2011-05-18 14:25:35 UTC
commit 27b03926618ddcafabb7b61e652fe6458b017b24
Author: Eric Anholt <eric@anholt.net>
Date:   Wed May 11 12:43:28 2011 -0700

    i965/fs: Fix discard and alpha test in 16-wide.
    As of gen6, alt-mode (which we use) MOVs of floats are not raw --
    they'll modify infs/nans.  This broke discard and alpha test in
    16-wide, where apparently the upper 8 bits of the pixel enables being
    set were causing the whole value to get trashed upon being moved.
    Treating the values as UD instead of float makes sure they get
    preserved.  While I'm here, replace the two 8-wide moves of the halves
    of the header with a single compressed move.
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=36648
    Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Comment 2 fangxun 2011-05-19 20:56:38 UTC
Verified with mesa master 116133af3499947500a6d0c877fbc8f564ee4c76.