System Environment: -------------------------- Libdrm: (master)libdrm-2.4.39-9-g2426a6a7112ae62755408a371831eddbe2d89d99 Mesa: (9.0)b1ce5749b996d6ce3dcf9bbd1537c46d14e62adb Xf86_video_intel: (master)2.20.8-28-geb667378543f97d7c7e7767daddbd9b39e07c1f8 Kernel: (drm-intel-fixes) f531dcb23f9a5c6ad77e451459df965dc9a0c0c8 Bug detailed description: ----------------------------- CPU hung when run Glbenchmark2.5.1(Revision b306a5) on SNB. It's work well on IVB and Piketon. There is no message when CPU hung. It's Mesa regression, as I know the good commit is 3a4ded6d1f67. If install new mesa, should reboot the machine to reproduce the problem. Reproduce steps: ---------------------------- 1, xinit& 2, ./GLBenchmark2.i386 -data ../../data/ -t 2000000
It also exists mesa master branch.
Works for me. I can't reproduce this.
We re-test it on the latest Mesa (master)6ef37f71b. It still exists GLBenchmark2.5.1 Revision b306a5 2012-09-18).
It still exists GLBenchmark2.5.1 revision 2332bc26. Libdrm: (master)libdrm-2.4.40-1-g7d42b49c0cf19dbb4531cd84efae51f95db2eea1 Mesa: (9.0)2332bc26d435e465a6f6571ab267db2a33ce05d2 Xf86_video_intel: (master)2.20.12-42-g94dd0b9ee9f55e7c09b8c0ee18939fa69ce66da2 Kernel: (drm-intel-fixes) 4a8dece21eea0ad6aca442272673d48693cd93b4
By bisected, show that 68216f35814ab8d292f37b8c0fa0a5f181b7f20d is the first bad commit. commit 68216f35814ab8d292f37b8c0fa0a5f181b7f20d Author: Eric Anholt <eric@anholt.net> Date: Thu May 17 22:03:32 2012 -0700 i965/gen6+: Add support for fast depth clears. Please see netconsole.log attached. BTW, it need to reboot before reproducing the bug.
Created attachment 71315 [details] netconsole.log when system hung
The problem will be fixed when disable RC6.
(In reply to comment #7) > The problem will be fixed when disable RC6. Can you read the value of register 0x2120, and if bit 8 isn't set, set it. You'll need the mask bit enable.
Created attachment 71522 [details] [review] implement Hiz w/a for msaa Kernel patch, please test.
Also: Is this an SNB GT1? Please spec the exact model and pci id of the VGA device.
(In reply to comment #9) With above patch, the problem still exists. Model:DELL U2410 pci id of the VGA device: 00:02.0 VGA compatible controller [0300]: Intel Corporation 2nd Generation Core Processor Family Integrated Graphics Controller [8086:0102] (rev 09)
(In reply to comment #8) > you read the value of register 0x2120, and if bit 8 isn't set, set it. > You'll need the mask bit enable. By intel_reg_read, the vaule of register 0x2120 : 0x6800, but I can't enable the bit8. ./intel_reg_write 0x2120 0x6880 Value before: 0x6800 Value after: 0x6800
In order to set bit 8, you need to set bit 8+16=24 as well---otherwise the write won't take effect. Or you could just set all of the high 16 bits. In other words, writing 0xffff6880 will change the value to 0x6880.
(In reply to comment #13) The valve could be write to 0x6880, but the problem still exists.
it works well with gnome-session.
Please test with the patch in #56416
(In reply to comment #16) > Please test with the patch in #56416 Verified with #56416 patch.
Let's keep the bug open until the patch committed to mesa master.
*** This bug has been marked as a duplicate of bug 56416 ***
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