Since the second slice is enabled, what is it exactly that you want. What we lack atm is slice shutdown.

the second slice is physically inside GT3 but not enabled by KMD. Want the 2nd slice to be enabled. thanks.

What does "intel_reg_write 0x138064 0x8" report?

Also, what exaxtly are the symptoms here? Hangs to due wrong threadcounts or just lack of performance?

to Wilson: the result is "Couldn't map MMIO region: Resource temporarily unavailable"

to Vetter: there is a performance gap between windows and linux, and we narrowed down to the missed 2nd slice support by comparing the source code with Windows KMD.

Now try again with the real intel-gpu-tools (i.e. built from http://cgit.freedesktop.org/xorg/app/intel-gpu-tools/).

$ sudo ./intel_reg_write 0x138064 0x8
Value before: 0xB
Value after: 0xB



btw, i tried to read this register in function i915_driver_load with the following source code, and the result is 0x8. Not know how the register changes from 0x8 to 0xB.
    int val = I915_READ(0x138064);
    printk("0x%x\n", val);

"lspci -vvvs 0:2" for the machine you are testing this on would be useful confirmation.

Since you got:

"Value before: 0xB"

I'd say that we don't have a bug here.
Please use $ sudo intel_reg_read 0x138064

This is more reliable than reading during load time.
If you still don't get 0xB with intel_reg_read so we do have a bug.
But 0x8 value is so strange it means all GT is off yet since

1:0 = 00: GT is powered off C6 or not yet booted

to Wilson:
$ lspci -vvvs 0:2
00:02.0 VGA compatible controller: Intel Corporation Device 0d26 (rev 07) (prog-if 00 [VGA controller])
        Subsystem: Intel Corporation Device 2212
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
        Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
        Latency: 0
        Interrupt: pin A routed to IRQ 46
        Region 0: Memory at c0000000 (64-bit, non-prefetchable) [size=4M]
        Region 2: Memory at b0000000 (64-bit, prefetchable) [size=256M]
        Region 4: I/O ports at 3000 [size=64]
        Expansion ROM at <unassigned> [disabled]
        Capabilities: <access denied>
        Kernel driver in use: i915
        Kernel modules: i915


to Vivi:
$ sudo ./intel_reg_read 0x138064
0x138064 : 0xB


And the register value read in function i915_driver_load is still 0x8.

When the GPU is out of rc6, both slices are enabled. So what leads you to think that the second slice is not supported?

I've confirmed that threads are being dispatched to both slices (by watching the PS Depth counts for the 2 slices, 0x22d8 and 0x22f8)