Bug 68040 - [HSW desktop/mobile bisected]WARNING: at drivers/gpu/drm/i915/i915_gem.c:3440 i915_gem_object_set_cache_level+0x1bd/0x1dc [i915]()
Summary: [HSW desktop/mobile bisected]WARNING: at drivers/gpu/drm/i915/i915_gem.c:3440...
Status: CLOSED FIXED
Alias: None
Product: DRI
Classification: Unclassified
Component: DRM/Intel (show other bugs)
Version: unspecified
Hardware: Other All
: medium major
Assignee: Chris Wilson
QA Contact: Intel GFX Bugs mailing list
URL:
Whiteboard:
Keywords:
: 68068 (view as bug list)
Depends on:
Blocks:
 
Reported: 2013-08-13 06:45 UTC by cancan,feng
Modified: 2017-10-06 14:44 UTC (History)
2 users (show)

See Also:
i915 platform:
i915 features:

Attachments
d46f1c boot dmesg (101.49 KB, text/plain)
2013-08-13 06:49 UTC, cancan,feng 		no flags Details
View All

Description cancan,feng 2013-08-13 06:45:35 UTC 
System Environment:
--------------------------------------------
Kernel: (drm-intel-next-queued)b8a1868b10bb4fe7fb7d283da5d56064b1a189f4
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Thu Aug 8 14:41:11 2013 +0100

    drm/i915: Allow the user to set bo into the DISPLAY cache domain

Bug detailed description:
--------------------------------------------
System boots with WARNING like this:

[    1.168965] WARNING: CPU: 1 PID: 1258 at drivers/gpu/drm/i915/i915_gem.c:3440 i915_gem_object_set_cache_level+0x1bd/0x1dc [i915]()

Bisected info:

d46f1c3f1372e3a72fab97c60480aa4a1084387f is the first bad commit
commit d46f1c3f1372e3a72fab97c60480aa4a1084387f
Author:     Chris Wilson <chris@chris-wilson.co.uk>
AuthorDate: Thu Aug 8 14:41:06 2013 +0100
Commit:     Daniel Vetter <daniel.vetter@ffwll.ch>
CommitDate: Sat Aug 10 11:24:18 2013 +0200

    drm/i915: Allow the GPU to cache stolen memory

    As a corollary to reviewing the interaction between LLC and our cache
    domains, the GPU PTE bits are independent of the CPU PAT bits. As such
    we can set the cache level on stolen memory based on how we wish the GPU
    to cache accesses to it. So we are free to set the same default cache
    levels as for normal bo, i.e. enable LLC cacheing by default where
    appropriate.

    Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
    Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
    Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Comment 1 cancan,feng 2013-08-13 06:49:26 UTC 
Created attachment 83996 [details]
d46f1c boot dmesg
Comment 2 Daniel Vetter 2013-08-13 06:53:46 UTC 
Please test this patch: https://patchwork.kernel.org/patch/2843023/
Comment 3 cancan,feng 2013-08-13 07:25:13 UTC 
(In reply to comment #2)
> Please test this patch: https://patchwork.kernel.org/patch/2843023/

This patch works well!! Call Trace can't be reproduced!!
Comment 4 Daniel Vetter 2013-08-13 15:50:20 UTC 
*** Bug 68068 has been marked as a duplicate of this bug. ***
Comment 5 Paulo Zanoni 2013-08-14 13:55:05 UTC 
(In reply to comment #3)
> (In reply to comment #2)
> > Please test this patch: https://patchwork.kernel.org/patch/2843023/
> 
> This patch works well!! Call Trace can't be reproduced!!

Patch merged, closing bug.

http://cgit.freedesktop.org/~danvet/drm-intel/commit/?h=drm-intel-next-queued&id=030c22d0c4a7a98968db820d3a9759197d580217

Thanks everybody for testing and fixing the bug,
Paulo
Comment 6 Elizabeth 2017-10-06 14:44:10 UTC 
Closing old verified.

Use of freedesktop.org services, including Bugzilla, is subject to our Code of Conduct. How we collect and use information is described in our Privacy Policy.