Created attachment 86779 [details] dmesg: testdisplay cause error and call trace Environment: ---------------------- Kernel: (drm-intel-next-queued)6d87c504b91510f6e3e933a9ee795e08bcb26a0d Author: Jesse Barnes <jbarnes@virtuousgeek.org> Date: Fri Sep 27 10:40:54 2013 -0700 drm/i915/vlv: reduce GT FIFO error info to a debug message Description: ----------------------- When both VGA and eDP plugged in, run testdisplay, eDP is good to display, but while switching to VGA, the process will be stuck at the first mode of VGA. Then check out the dmesg, there's Error and call trace in it. I have tested many older kernels and can't find a good commit, it's not a regression. Testdisplay works well if we only plugged in one pipe. Our baytrail only support eDP and VGA. It's an unique issue on Baytrail. Error: ----------------------- [ 186.312961] [drm:intel_edp_psr_match_conditions], PSR not supported on this p latform [ 186.312970] [drm:intel_crtc_mode_set], [ENCODER:10:DAC-10] set [MODE:0:1680x1 050] [ 186.316857] [drm:vlv_enable_pll] *ERROR* DPLL 0 failed to lock [ 186.317531] [drm:g4x_check_srwm], SR watermark: display plane 107, cursor 6 [ 186.317537] [drm:g4x_check_srwm], SR watermark: display plane 212, cursor 10 [ 186.317543] [drm:valleyview_update_wm], Setting FIFO watermarks - A: plane=93, cursor=6, B: plane=2, cursor=2, SR: plane=107, cursor=10 [ 186.368849] [drm:ironlake_wait_for_vblank], vblank wait timed out Call Trace: ---------------------- There's three kind of call trace, please see them from dmesg.
The problem stems from a failed DPIO causing a divide-by-zero whilst holding the mutex. The machine lockup will be fixed by Jesse's WARN(div-by-zero) but the system is still snafu.
Should be fixed by the DPLL fixup: commit 559a81bdaee1763313d7305521b9b0ae5a1b99c1 Author: Jesse Barnes <jbarnes@virtuousgeek.org> Date: Tue Oct 1 10:41:38 2013 -0700 i915/vlv: untangle integrated clock source handling v4
Test with latest -next-queued, this issue been fixed. Verified here.
Closing verified+fixed.
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