Bug 84826 - [BSW Bisected]Piglit shaders_glsl-routing fails intermittently
Summary: [BSW Bisected]Piglit shaders_glsl-routing fails intermittently
Status: RESOLVED FIXED
Alias: None
Product: Mesa
Classification: Unclassified
Component: Drivers/DRI/i965 (show other bugs)
Version: unspecified
Hardware: All Linux (All)
: medium normal
Assignee: Ben Widawsky
QA Contact: Intel 3D Bugs Mailing List
URL:
Whiteboard:
Keywords:
Depends on:
Blocks:
 
Reported: 2014-10-09 06:45 UTC by lu hua
Modified: 2016-11-03 15:55 UTC (History)
3 users (show)

See Also:
i915 platform:
i915 features:

Attachments

Description lu hua 2014-10-09 06:45:49 UTC 
System Environment:
--------------------------
Platform: BSW
Libdrm:		(master)libdrm-2.4.58-4-g00847fa48b83a85b0cb882594a12ed1511f780db
Mesa:		(master)16b53005a7df4249fecb6641af0934c32181fdea
Xserver:	(master)xorg-server-1.16.0-386-g95a5b92e37f73f497d547fd91c543c16d2cc73de
Xf86_video_intel:(master)2.99.916-84-gec2b9ac81aed0d2dda2948171ca1c260184bf221
Libva:		(master)cdf8636d5fc5b1558570fede347e1599e0d6af3d
Libva_intel_driver:(master)f11176415ec26eb5960ba6841d2d9c22f2cabc60
Kernel:   (drm-intel-nightly)eabc0c8db15f9ba4d727aee5e0612a68cafe1ab5

Bug detailed description:
-----------------------------
It fails on BSW with mesa master branch.
good commit: fc4b5b85ce88f607d29242e6b3667bad6457a871
bad commit: 16b53005a7df4249fecb6641af0934c32181fdea

output:
Test: VS(C0 C1 T0 T1 T2 T3 T4 T5)
      FS(C0 -- T0 -- T2 -- T4 T5)

Test: VS(C0 C1 T0 T1 T2 T3 T4 T5)
      FS(-- C1 T0 T1 -- -- T4 --)

Test: VS(C0 C1 T0 T1 T2 T3 T4 T5)
      FS(C0 C1 -- -- T2 -- T4 T5)

Test: VS(C0 C1 T0 T1 T2 T3 T4 T5)
      FS(-- C1 -- -- T2 T3 -- --)

Test: VS(C0 -- T0 -- T2 -- T4 T5)
      FS(C0 C1 T0 T1 T2 T3 T4 T5)
Probe color at (67,127)
  Expected: 0.200000 0.300000 0.400000
  Observed: 0.200000 0.298039 0.000000

Test: VS(-- C1 T0 T1 -- -- T4 --)
      FS(C0 C1 T0 T1 T2 T3 T4 T5)

Test: VS(C0 C1 -- -- -- T3 -- T5)
      FS(C0 C1 T0 T1 T2 T3 T4 T5)

Test: VS(-- C1 -- -- T2 T3 T4 --)
      FS(C0 C1 T0 T1 T2 T3 T4 T5)

Test: VS(C0 -- T0 -- T2 -- T4 T5)
      FS(C0 C1 T0 T1 -- -- T4 --)

Test: VS(C0 C1 -- T1 -- -- T4 T5)
      FS(-- C1 -- T1 T2 T3 T4 --)

Test: VS(-- C1 T0 -- T2 T3 -- T5)
      FS(-- C1 -- T1 T2 T3 T4 T5)

Test: VS(C0 C1 T0 -- T2 T3 T4 T5)
      FS(C0 -- T0 -- -- T3 -- T5)
PIGLIT: {"result": "fail" }

Reproduce steps:
---------------------------- 
1. xinit
2. bin/glsl-routing -fbo -auto
Comment 1 Tapani Pälli 2014-10-10 04:55:12 UTC 
Lu Hua, can you bisect this? There's quite a few commits in between good and bad described in the bug description.
Comment 2 lu hua 2014-10-10 04:57:19 UTC 
(In reply to Tapani Pälli from comment #1)
> Lu Hua, can you bisect this? There's quite a few commits in between good and
> bad described in the bug description.

OK. I will bisect it.
Comment 3 Kenneth Graunke 2014-10-10 07:40:10 UTC 
Does it always fail?  I think I've seen this test pass sometimes and fail other times.
Comment 4 lu hua 2014-10-10 07:46:28 UTC 
(In reply to Kenneth Graunke from comment #3)
> Does it always fail?  I think I've seen this test pass sometimes and fail
> other times.

It works well on fc4b5b85ce88f607d29242e6b3667bad6457a871.
Comment 5 lu hua 2014-10-11 08:23:47 UTC 
Bisect shows: 7210583eb84a5d49803dbe37b0960373b4224d10 is the first bad commit.
commit 7210583eb84a5d49803dbe37b0960373b4224d10
Author:     Jason Ekstrand <jason.ekstrand@intel.com>
AuthorDate: Mon Aug 18 14:27:55 2014 -0700
Commit:     Jason Ekstrand <jason.ekstrand@intel.com>
CommitDate: Tue Sep 30 10:29:14 2014 -0700

    i965/fs_reg: Allocate double the number of vgrfs in SIMD16 mode

    This is actually the squash of a bunch of different changes.  Individual
    commit titles follow:

    i965/fs: Always 2-align registers SIMD16 for gen <= 5

    i965/fs: Use the register width when applying offsets

       This reworks both byte_offset() and offset() to be more intelligent.
       The byte_offset() function now supports offsets bigger than 32. The
       offset() function uses the byte_offset() function together with the
       register width and the type size to offset the register by the correct
       amount.

    i965/fs: Change regs_read to be in hardware registers

    i965/fs: Change regs_written to be actual hardware registers

    i965/fs: Properly handle register widths in LOAD_PAYLOAD

       The LOAD_PAYLOAD instruction is a bit special because it collects a
       bunch of registers (with possibly different widths) into a single
       payload block.  Once the payload is constructed, it's treated as a
       single block of data and most of the information such as register widths
       doesn't matter anymore.  In particular, the offset of any particular
       source register is the accumulation of the sizes of the previous source
       registers.
Comment 6 Jason Ekstrand 2014-10-30 17:28:30 UTC 
This should have been fixed by the spilling fixes I pushed to master this week.  Reopen if it isn't.
Comment 7 lu hua 2014-11-03 08:18:03 UTC 
It still fails on latest mesa master branch(52576dcb882202ea1e2c239):
output:
Test: VS(C0 C1 T0 T1 T2 T3 T4 T5)
      FS(C0 -- T0 -- T2 -- T4 T5)

Test: VS(C0 C1 T0 T1 T2 T3 T4 T5)
      FS(-- C1 T0 T1 -- -- T4 --)

Test: VS(C0 C1 T0 T1 T2 T3 T4 T5)
      FS(C0 C1 -- -- T2 -- T4 T5)

Test: VS(C0 C1 T0 T1 T2 T3 T4 T5)
      FS(-- C1 -- -- T2 T3 -- --)

Test: VS(C0 -- T0 -- T2 -- T4 T5)
      FS(C0 C1 T0 T1 T2 T3 T4 T5)
Probe color at (67,127)
  Expected: 0.200000 0.300000 0.400000
  Observed: 0.200000 0.298039 0.000000
Probe color at (187,127)
  Expected: 0.600000 0.700000 0.800000
  Observed: 0.000000 0.000000 0.000000

Test: VS(-- C1 T0 T1 -- -- T4 --)
      FS(C0 C1 T0 T1 T2 T3 T4 T5)
Probe color at (187,157)
  Expected: 0.600000 0.700000 0.800000
  Observed: 0.000000 0.000000 0.000000

Test: VS(C0 C1 -- -- -- T3 -- T5)
      FS(C0 C1 T0 T1 T2 T3 T4 T5)

Test: VS(-- C1 -- -- T2 T3 T4 --)
      FS(C0 C1 T0 T1 T2 T3 T4 T5)

Test: VS(C0 -- T0 -- T2 -- T4 T5)
      FS(C0 C1 T0 T1 -- -- T4 --)

Test: VS(C0 C1 -- T1 -- -- T4 T5)
      FS(-- C1 -- T1 T2 T3 T4 --)

Test: VS(-- C1 T0 -- T2 T3 -- T5)
      FS(-- C1 -- T1 T2 T3 T4 T5)

Test: VS(C0 C1 T0 -- T2 T3 T4 T5)
      FS(C0 -- T0 -- -- T3 -- T5)
PIGLIT: {"result": "fail" }
Comment 8 Ben Widawsky 2014-11-25 20:03:56 UTC 
Can you please try
INTEL_DEBUG=no16 ./bin/glsl-routing -fbo -auto

This should pass. I have a hunch
Comment 9 lu hua 2014-11-26 07:27:28 UTC 
(In reply to Ben Widawsky from comment #8)
> Can you please try
> INTEL_DEBUG=no16 ./bin/glsl-routing -fbo -auto
> 
> This should pass. I have a hunch

Yes, it's pass.
[root@x-bsw01 piglit]# INTEL_DEBUG=no16 ./bin/glsl-routing -fbo -auto

Test: VS(C0 C1 T0 T1 T2 T3 T4 T5)
      FS(C0 -- T0 -- T2 -- T4 T5)

Test: VS(C0 C1 T0 T1 T2 T3 T4 T5)
      FS(-- C1 T0 T1 -- -- T4 --)

Test: VS(C0 C1 T0 T1 T2 T3 T4 T5)
      FS(C0 C1 -- -- T2 -- T4 T5)

Test: VS(C0 C1 T0 T1 T2 T3 T4 T5)
      FS(-- C1 -- -- T2 T3 -- --)

Test: VS(C0 -- T0 -- T2 -- T4 T5)
      FS(C0 C1 T0 T1 T2 T3 T4 T5)

Test: VS(-- C1 T0 T1 -- -- T4 --)
      FS(C0 C1 T0 T1 T2 T3 T4 T5)

Test: VS(C0 C1 -- -- -- T3 -- T5)
      FS(C0 C1 T0 T1 T2 T3 T4 T5)

Test: VS(-- C1 -- -- T2 T3 T4 --)
      FS(C0 C1 T0 T1 T2 T3 T4 T5)

Test: VS(C0 -- T0 -- T2 -- T4 T5)
      FS(C0 C1 T0 T1 -- -- T4 --)

Test: VS(C0 C1 -- T1 -- -- T4 T5)
      FS(-- C1 -- T1 T2 T3 T4 --)

Test: VS(-- C1 T0 -- T2 T3 -- T5)
      FS(-- C1 -- T1 T2 T3 T4 T5)

Test: VS(C0 C1 T0 -- T2 T3 T4 T5)
      FS(C0 -- T0 -- -- T3 -- T5)
PIGLIT: {"result": "pass" }
Comment 10 Ben Widawsky 2014-12-01 20:13:13 UTC 
Wendy, why is this "major" now?
Comment 11 Gordon Jin 2014-12-02 00:58:57 UTC 
(In reply to Ben Widawsky from comment #10)
> Wendy, why is this "major" now?

I see this as the only Mesa regression on BSW specific, and the only Mesa one in our BSW top bug list.
You could change it if you don't think it important.
Comment 12 Ben Widawsky 2014-12-03 06:58:36 UTC 
With mesa master, do you still have all 3 failures?

> Test: VS(C0 -- T0 -- T2 -- T4 T5)
>       FS(C0 C1 T0 T1 T2 T3 T4 T5)
> Probe color at (67,127)
>   Expected: 0.200000 0.300000 0.400000
>   Observed: 0.200000 0.298039 0.000000
> Probe color at (187,127)
>   Expected: 0.600000 0.700000 0.800000
>   Observed: 0.000000 0.000000 0.000000
> 
> Test: VS(-- C1 T0 T1 -- -- T4 --)
>       FS(C0 C1 T0 T1 T2 T3 T4 T5)
> Probe color at (187,157)
>   Expected: 0.600000 0.700000 0.800000
>   Observed: 0.000000 0.000000 0.000000
>
Comment 13 lu hua 2014-12-03 07:25:42 UTC 
Test latest mesa master branch.
output:
libGL: OpenDriver: trying /opt/X11R7/lib/dri/tls/i965_dri.so
libGL: OpenDriver: trying /opt/X11R7/lib/dri/i965_dri.so

Test: VS(C0 C1 T0 T1 T2 T3 T4 T5)
      FS(C0 -- T0 -- T2 -- T4 T5)

Test: VS(C0 C1 T0 T1 T2 T3 T4 T5)
      FS(-- C1 T0 T1 -- -- T4 --)

Test: VS(C0 C1 T0 T1 T2 T3 T4 T5)
      FS(C0 C1 -- -- T2 -- T4 T5)

Test: VS(C0 C1 T0 T1 T2 T3 T4 T5)
      FS(-- C1 -- -- T2 T3 -- --)

Test: VS(C0 -- T0 -- T2 -- T4 T5)
      FS(C0 C1 T0 T1 T2 T3 T4 T5)
Probe color at (67,127)
  Expected: 0.200000 0.300000 0.400000
  Observed: 0.200000 0.298039 0.000000

Test: VS(-- C1 T0 T1 -- -- T4 --)
      FS(C0 C1 T0 T1 T2 T3 T4 T5)

Test: VS(C0 C1 -- -- -- T3 -- T5)
      FS(C0 C1 T0 T1 T2 T3 T4 T5)

Test: VS(-- C1 -- -- T2 T3 T4 --)
      FS(C0 C1 T0 T1 T2 T3 T4 T5)

Test: VS(C0 -- T0 -- T2 -- T4 T5)
      FS(C0 C1 T0 T1 -- -- T4 --)

Test: VS(C0 C1 -- T1 -- -- T4 T5)
      FS(-- C1 -- T1 T2 T3 T4 --)

Test: VS(-- C1 T0 -- T2 T3 -- T5)
      FS(-- C1 -- T1 T2 T3 T4 T5)

Test: VS(C0 C1 T0 -- T2 T3 T4 T5)
      FS(C0 -- T0 -- -- T3 -- T5)
PIGLIT: {"result": "fail" }
Comment 14 Ben Widawsky 2014-12-04 19:40:16 UTC 
I have some evidence now that this is also a dupe on 84777. I'd like to leave it as a separate bug still for now (since the fact that it's a regression is weird), but I'd like to lower the priority.

Please adjust if you disagree.
Comment 15 Ben Widawsky 2014-12-04 23:18:16 UTC 
Can you please test my mesa branch?
http://cgit.freedesktop.org/~bwidawsk/mesa/log/?h=qw-mul
Comment 16 lu hua 2014-12-05 06:06:46 UTC 
(In reply to Ben Widawsky from comment #15)
> Can you please test my mesa branch?
> http://cgit.freedesktop.org/~bwidawsk/mesa/log/?h=qw-mul

Hi Ben,
I test the patch(https://bugs.freedesktop.org/show_bug.cgi?id=84777#c23), it still fail. Still need to test your branch? If so, I will build it.
Thanks.
Comment 17 Ben Widawsky 2014-12-05 06:21:30 UTC 
Ken thinks this test might have intermittent failures. Can you run multiple times on both BDW and CHV and see if BDW is 100% pass, and CHV is 100% fail.
Comment 18 lu hua 2014-12-05 08:21:57 UTC 
(In reply to Ben Widawsky from comment #17)
> Ken thinks this test might have intermittent failures. Can you run multiple
> times on both BDW and CHV and see if BDW is 100% pass, and CHV is 100% fail.

Run 50 cycles on BDW and BSW, it always fail on BSW and always pass on BDW.
Comment 19 Ben Widawsky 2014-12-05 20:40:25 UTC 
Can you please test this on HSW as well? Thanks.
Comment 20 lu hua 2014-12-08 01:45:17 UTC 
It sporadically fails on HSW, fail rate 1/5.

Test: VS(C0 -- T0 -- T2 -- T4 T5)
      FS(C0 C1 T0 T1 T2 T3 T4 T5)
Probe color at (217,127)
  Expected: 0.700000 0.800000 0.900000
  Observed: 0.698039 0.000000 0.898039

Test: VS(-- C1 T0 T1 -- -- T4 --)
      FS(C0 C1 T0 T1 T2 T3 T4 T5)
Comment 21 Ben Widawsky 2015-03-06 04:58:39 UTC 
Still present?
Comment 22 lu hua 2015-03-09 02:58:42 UTC 
still exist.
Test: VS(C0 C1 T0 T1 T2 T3 T4 T5)
      FS(C0 -- T0 -- T2 -- T4 T5)

Test: VS(C0 C1 T0 T1 T2 T3 T4 T5)
      FS(-- C1 T0 T1 -- -- T4 --)

Test: VS(C0 C1 T0 T1 T2 T3 T4 T5)
      FS(C0 C1 -- -- T2 -- T4 T5)

Test: VS(C0 C1 T0 T1 T2 T3 T4 T5)
      FS(-- C1 -- -- T2 T3 -- --)

Test: VS(C0 -- T0 -- T2 -- T4 T5)
      FS(C0 C1 T0 T1 T2 T3 T4 T5)
Probe color at (7,127)
  Expected: 0.000000 0.100000 0.200000
  Observed: 0.000000 0.098039 0.000000
Probe color at (217,127)
  Expected: 0.700000 0.800000 0.900000
  Observed: 0.000000 0.000000 0.000000

Test: VS(-- C1 T0 T1 -- -- T4 --)
      FS(C0 C1 T0 T1 T2 T3 T4 T5)

Test: VS(C0 C1 -- -- -- T3 -- T5)
      FS(C0 C1 T0 T1 T2 T3 T4 T5)

Test: VS(-- C1 -- -- T2 T3 T4 --)
      FS(C0 C1 T0 T1 T2 T3 T4 T5)

Test: VS(C0 -- T0 -- T2 -- T4 T5)
      FS(C0 C1 T0 T1 -- -- T4 --)

Test: VS(C0 C1 -- T1 -- -- T4 T5)
      FS(-- C1 -- T1 T2 T3 T4 --)

Test: VS(-- C1 T0 -- T2 T3 -- T5)
      FS(-- C1 -- T1 T2 T3 T4 T5)

Test: VS(C0 C1 T0 -- T2 T3 T4 T5)
      FS(C0 -- T0 -- -- T3 -- T5)
PIGLIT: {"result": "fail" }
Comment 23 Alejandro Piñeiro (freenode IRC: apinheiro) 2015-03-12 10:35:05 UTC 
(In reply to lu hua from comment #20)
> It sporadically fails on HSW, fail rate 1/5.

A little update as I have been trying based on this recent:
09b03254091d054800834ddee604885a1093673f (Mar 11)

On a haswell machine.

In my case, I experienced ~20 fails while doing 1000 runs checks, meaning an aprox 2/100 frequency. That is really lower that 1/5. Just in case someone tests again and conclude that the test pass now.
Comment 24 cprigent 2015-10-10 17:19:04 UTC 
Not reproduced on BSW with Mesa 11.0.2:

Hardware:
Platform: Braswell M 
CPU : Intel(R) Celeron N3060 1.60GHz @ 1.6 GHz (family: 6, model: 76 stepping: 4)
SoC : BSW C0
QDF : K6XC
CRB : BRASWELL RVP Fab2
Mandatory Reworks : All Feature Reworks: F28, F32, F33, F35, F37
Optional reworks : O-01a; O-02, O-03 

Software :
Linux distribution: Ubuntu 14.04 LTS 64 bits 
BIOS : BRAS.X64.B084.R00.1508310642
TXE FW : 2.0.0.2073
Ksc : 1.08

kernel drm-intel-nightly 4.3.0-rc3 eb69e51
cairo: (HEAD, tag: 1.14.2) 93422b3cb5e0ef8104b8194c8873124ce2f5ea2d from
git://git.freedesktop.org/git/cairo
drm: (HEAD, tag: libdrm-2.4.64, tag: 2.4.64)
ab2fadabde3829b1ec56bd4756165dd9bd281488 from
git://git.freedesktop.org/git/mesa/drm
intel-driver: (HEAD, origin/master, origin/HEAD, master)
2a72f99d24714f2a58f400ef63b913d4cf9080b3 from
git://git.freedesktop.org/git/vaapi/intel-driver
libva: (HEAD, tag: libva-1.6.1, origin/v1.6-branch)
613eb962b45fbbd1526d751e88e0d8897af6c0e0 from
git://git.freedesktop.org/git/vaapi/libva
mesa: (HEAD, tag: mesa 11.0.2) 51e0b06d9916e126060c0d218de1aaa4e5a4ce26  
 from git://git.freedesktop.org/git/mesa/mesa
xf86-video-intel: (HEAD, origin/master, origin/HEAD, master)
f0fd4d500de03c30c7ce19915f85acadd1ca4e5d from
git://git.freedesktop.org/git/xorg/driver/xf86-video-intel
xserver: (HEAD, tag: xorg-server-1.17.2) 2123f7682d522619f101b05fb75efa75dabbe371 from git://git.freedesktop.org/git/xorg/xserver
Comment 25 cprigent 2015-10-10 17:19:18 UTC 
So closed
Comment 26 Ben Widawsky 2015-10-10 17:24:27 UTC 
(In reply to cprigent from comment #24)
> Not reproduced on BSW with Mesa 11.0.2:
> 

How many times did you run it? It's an intermittent failure.

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