Created attachment 108595 [details]
graphics corruption video

Created attachment 108596 [details]
graphics corruption video

The issue is that the cache setting bits in the Global GTT PTE are ignored. At best we can throw a warning that setting i915.enable_ppgtt=0 is a bad idea, or we might be able to disable the render caches using a debug register. Fundamentally though it is a CANTFIX/WONTFIX.

(In reply to Chris Wilson from comment #3)
> The issue is that the cache setting bits in the Global GTT PTE are ignored.
> At best we can throw a warning that setting i915.enable_ppgtt=0 is a bad
> idea, or we might be able to disable the render caches using a debug
> register. Fundamentally though it is a CANTFIX/WONTFIX.

Is the problem caused by this nice piece if hardware design?
"***For GGTT, there is NO pat_sel[2:0] from the entry, so RTL will always use the value corresponding to pat_sel = 000***"

If so then I think we might need to make PAT entry 0 UC, which is a bit sad since it's the opposite of how the CPU PAT is set up, but at least it would give correct behaviour. The only concern is that all GGTT accesses will then be UC which I suppose could lead to some performance issues. But MOCS can still override it so anything that has MOCS could still get WB if needed.

James, could you please try this?

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index cb7adab..a82b8a7 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1911,7 +1911,7 @@ static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
 {
        uint64_t pat;
 
-       pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC)     | /* for normal objects, no eLLC */
+       pat = GEN8_PPAT(0, GEN8_PPAT_UC)     | /* TEST for bug 85576 */

Yep, that fixes it!

Fixed in drm-intel-fixes by

commit d6a8b72edc92471283925ceb4ba12799b67c3ff8
Author: Rodrigo Vivi <rodrigo.vivi@intel.com>
Date:   Wed Nov 5 16:56:36 2014 -0800

    drm/i915: Disable caches for Global GTT.