==System Environment== -------------------------- Regression: yes good commit: 6476486cb3570d3662e4a3870b884e75d35d1072 bad commit: 421d82916774361a4840018fc3ab3a15751c3ea6 Non-working platforms: BYT ==kernel== -------------------------- drm-intel-nightly/bd21cf795cf5dc278f1451d0f7a597cb1d13c2ba ==Bug detailed description== It fails on BYT with -queued and -nightly kernel. It also has bug 84859, add i915.enable_ppgtt=1, it still fails. output: IGT-Version: 1.8-gcba3088 (x86_64) (Linux: 3.18.0-rc2_drm-intel-nightly_bd21cf_20141030+ x86_64) Test assertion failure function do_test, file gem_reloc_vs_gpu.c:221: Failed assertion: test == 0xdeadbeef mismatch in buffer 1: 0x00000000 instead of 0xdeadbeef Subtest faulting-reloc: FAIL (0.481s) dmesg: [ 243.292762] gem_reloc_vs_gpu: executing [ 243.304659] [drm:i915_gem_open] [ 243.305204] [drm:i915_gem_open] [ 243.305439] gem_reloc_vs_gpu: starting subtest faulting-reloc [ 243.438118] [drm:valleyview_set_rps] GPU freq request from 646 MHz (214) to 667 MHz (215) [ 243.521711] [drm:valleyview_set_rps] GPU freq request from 667 MHz (215) to 646 MHz (214) [ 243.607257] [drm:valleyview_set_rps] GPU freq request from 646 MHz (214) to 667 MHz (215) [ 243.692318] [drm:valleyview_set_rps] GPU freq request from 667 MHz (215) to 708 MHz (217) [ 243.776392] [drm:valleyview_set_rps] GPU freq request from 708 MHz (217) to 791 MHz (221) [ 243.861469] [drm:valleyview_set_rps] GPU freq request from 791 MHz (221) to 854 MHz (224) [ 249.935839] [drm] stuck on blitter ring [ 249.942053] [drm] GPU HANG: ecode 2:0x21524118, in gem_reloc_vs_gp [4378], reason: Ring hung, action: reset [ 249.942817] [drm:i915_error_work_func] resetting chip [ 249.944414] drm/i915: Resetting chip after gpu hang [ 249.944426] [drm:init_status_page] render ring hws offset: 0x00409000 [ 249.946426] [drm:init_status_page] bsd ring hws offset: 0x0042d000 [ 249.946608] [drm:init_status_page] blitter ring hws offset: 0x00450000 [ 249.946648] [drm:i9xx_update_primary_plane] Writing base 00473000 00000000 0 0 5504 [ 249.953595] [drm:intel_crtc_set_config] [CRTC:8] [FB:35] #connectors=1 (x y) (0 0) [ 249.953606] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0 [ 249.953611] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:eDP-1] to [CRTC:8] [ 249.953617] [drm:intel_crtc_set_config] [CRTC:13] [NOFB] [ 249.953621] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:13], mode_changed=0, fb_changed=0 [ 249.953625] [drm:intel_modeset_stage_output_state] [CONNECTOR:28:eDP-1] to [CRTC:8] [ 251.937584] [drm:intel_print_rc6_info] Enabling RC6 states: RC6 on [ 251.939040] [drm:valleyview_enable_rps] GPLL enabled? yes [ 251.939045] [drm:valleyview_enable_rps] GPU status: 0x0000e0d0 [ 251.939049] [drm:valleyview_enable_rps] current GPU freq: 854 MHz (224) [ 251.939053] [drm:valleyview_enable_rps] setting GPU freq to 646 MHz (214) [ 251.939057] [drm:valleyview_set_rps] GPU freq request from 854 MHz (224) to 646 MHz (214) ==Reproduce steps== ---------------------------- 1. ./gem_reloc_vs_gpu --run-subtest faulting-reloc
add i915.enable_ppgtt=0, it works well.
*** Bug 85673 has been marked as a duplicate of this bug. ***
*** Bug 85672 has been marked as a duplicate of this bug. ***
Please try http://patchwork.freedesktop.org/patch/36045/
(In reply to Chris Wilson from comment #4) > Please try http://patchwork.freedesktop.org/patch/36045/ Fixed by this patch.
commit 7ad6e04a3d0e7c24fbb14bd7dd2f3d7168423318 Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Fri Oct 31 13:53:52 2014 +0000 drm/i915: Only mark as map-and-fenceable when bound into the GGTT We use the obj->map_and_fenceable hint for when we already have a valid mapping of this object in the aperture. This hint can only apply to the GGTT and not to the aliasing-ppGTT. One user of the hint is execbuffer relocation, which began to fail when it tried to follow the hint and perform the relocate through the non-existent GGTT mapping. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85671 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Verified.Fixed.
Closing old verified.
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