Created attachment 110648 [details] Displayed result with 3.18 On Acer TravelMate 66x with i855GM switching from 3.17 to 3.18 kernel scanout to LVDS becomes mis-configured. It looks like pixels are being displayed "interlaced" both horizontally and vertically so that first pixel is at its expected location, pixel right of it is two pixes further to the right, pixel at half screen (or is it 1/4 of screen) is located right below first pixel. See screenshots for visual representation. Further debug details will follow with some delay, as well as bisection.
Created attachment 110649 [details] Expected result, with 3.17
Created attachment 110650 [details] intel_reg_dump, with 3.17
Kernel log extract, with 3.18: [ 0.893782] Linux agpgart interface v0.103 [ 0.893893] agpgart-intel 0000:00:00.0: Intel 855GM Chipset [ 0.893960] agpgart-intel 0000:00:00.0: detected gtt size: 131072K total, 131072K mappable [ 0.894634] agpgart-intel 0000:00:00.0: detected 32768K stolen memory [ 0.894992] agpgart-intel 0000:00:00.0: AGP aperture is 128M @ 0xe8000000 [ 0.895201] [drm] Initialized drm 1.1.0 20060810 [ 0.897913] [drm] Memory usable by graphics device = 128M [ 0.897973] [drm] Replacing VGA console driver [ 0.898927] Console: switching to colour dummy device 80x25 [ 0.901093] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). [ 0.901109] [drm] Driver supports precise vblank timestamp query. [ 0.901357] vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem [ 0.990220] [drm] GMBUS [i915 gmbus panel] timed out, falling back to bit banging on pin 3 [ 1.020916] [drm:i9xx_set_fifo_underrun_reporting] *ERROR* pipe A underrun [ 1.047516] [drm] initialized overlay support [ 1.047632] [drm] Initialized i915 1.6.0 20140905 for 0000:00:02.0 on minor 0 [ 1.100281] [drm] GMBUS [i915 gmbus vga] timed out, falling back to bit banging on pin 2 [ 1.121264] [drm:i9xx_set_fifo_underrun_reporting] *ERROR* pipe A underrun [ 1.200224] [drm] GMBUS [i915 gmbus dpb] timed out, falling back to bit banging on pin 5 [ 1.215077] fbcon: inteldrmfb (fb0) is primary device [ 1.810166] Console: switching to colour frame buffer device 175x65 [ 1.820984] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device [ 1.821053] i915 0000:00:02.0: registered panic notifier [ 122.817020] [drm:i9xx_check_fifo_underruns] *ERROR* pipe B underrun [ 122.831035] [drm:i9xx_set_fifo_underrun_reporting] *ERROR* pipe A underrun [ 155.129274] [drm:i9xx_set_fifo_underrun_reporting] *ERROR* pipe A underrun [ 432.772681] [drm:i9xx_set_fifo_underrun_reporting] *ERROR* pipe A underrun [ 498.863614] [drm:i9xx_set_fifo_underrun_reporting] *ERROR* pipe A underrun [ 524.688752] [drm:i9xx_set_fifo_underrun_reporting] *ERROR* pipe A underrun [ 526.163628] [drm:i9xx_set_fifo_underrun_reporting] *ERROR* pipe A underrun [ 543.921330] [drm:i9xx_set_fifo_underrun_reporting] *ERROR* pipe A underrun [ 545.472861] [drm:i9xx_set_fifo_underrun_reporting] *ERROR* pipe A underrun [ 562.710908] [drm:i9xx_set_fifo_underrun_reporting] *ERROR* pipe A underrun [ 565.496726] [drm:i9xx_check_fifo_underruns] *ERROR* pipe B underrun [ 565.510848] [drm:i9xx_set_fifo_underrun_reporting] *ERROR* pipe A underrun [ 624.522935] [drm:i9xx_set_fifo_underrun_reporting] *ERROR* pipe B underrun
Created attachment 110651 [details] intel_reg_dump, with 3.18
Better description of the output with 3.18: About top half of framebuffer is visible though pixel lines are not wrapped as one would expect, they are wrapped somewhere around the middle (but not exactly) so each pixel line from framebuffer fills two lines on monitor. From looking at difference between reg_dumper outputs under 3.17 and 3.18, the major difference is: 3.17: DSPASTRIDE: 0x00002000 (8192 bytes) 3.18: DSPASTRIDE: 0x00001600 (5632 bytes) Full difference: 3.17: DSPASTRIDE: 0x00002000 (8192 bytes) DSPABASE: 0x01000000 DSPBCNTR: 0x58000000 (disabled, pipe A) DSPBBASE: 0x00020000 VGACNTRL: 0x80000000 (disabled) 3.18 DSPASTRIDE: 0x00001600 (5632 bytes) DSPABASE: 0x00020000 DSPBCNTR: 0x00000000 (disabled, pipe A) DSPBBASE: 0x00000000 VGACNTRL: 0xe104008e (disabled)
Can you try this 'intel_reg_write 0x20cc 0x40000' ?
(In reply to Ville Syrjala from comment #6) > Can you try this 'intel_reg_write 0x20cc 0x40000' ? This made no visual change, no any difference in intel_reg_dumper output. On execution it reported old value of 0x4 and new value of 0x0. Going to perform bisection unless you have some better/quicker suggestion.
(In reply to Bruno from comment #7) > (In reply to Ville Syrjala from comment #6) > > Can you try this 'intel_reg_write 0x20cc 0x40000' ? > > This made no visual change, no any difference in intel_reg_dumper output. > > On execution it reported old value of 0x4 and new value of 0x0. So not trickle feed related. > > Going to perform bisection unless you have some better/quicker suggestion. I guess it wouldn't hurt to check the watermarks too. Any difference between the kernels with this? intel_reg_read -c 2 0x20d8 If that's not it either, then a bisect would be appreciated.
> I guess it wouldn't hurt to check the watermarks too. Any difference between > the kernels with this? > intel_reg_read -c 2 0x20d8 There is: - 3.17 0x20D8 : 0x1080101 ^ 0x20DC : 0x102 - 3.18 0x20D8 : 0x11F0108 ^ 0x20DC : 0x102 > If that's not it either, then a bisect would be appreciated. Operation in progress :) 2/13 iterations done
Done bisecting. Offending commit is: commit 69769f9a422bfc62e17399da3590c5e31ac37f24 Author: Ville Syrjälä <ville.syrjala@linux.intel.com> Date: Fri Aug 15 01:22:08 2014 +0300 drm/i915: Preserve VGACNTR bits from the BIOS My Fujistsu-Siemens Lifebook S6010 doesn't like to resume from S3 unless VGACNTR has been restore to the original value. The BIOS value in this case was 0x0124008E. Setting the "VGA disable" bit doesn't interfere with the S3 resume fortunately. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Tested-by: Thomas Richter <richter@rus.uni-stuttgart.de> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reverting just this commit from 3.18 makes the display issue go away. It seems i915_vgacntrl_reg() [VGACNTRL on i855GM] still has some effect on LVDS configuration when VGA_DISP_DISABLE bit is set. In i915_reg.h the following bits are defined: # define VGA_DISP_DISABLE (1 << 31) # define VGA_2X_MODE (1 << 30) # define VGA_PIPE_B_SELECT (1 << 29) Of those bits VGA_2X_MODE might very well be related to the end result I'm seeing here. (my VGA mode is set to 2X mode if I'm not mistaken...) I'm going to check VGACNTRL values as handled by this commit and check if zeroing VGA_2X_MODE or VGA_PIPE_B_SELECT is sufficient to get proper output.
Note: the pipe underrun complaints are still there though: [ 0.894671] [drm] Initialized drm 1.1.0 20060810 [ 0.897376] [drm] Memory usable by graphics device = 128M [ 0.897437] [drm] Replacing VGA console driver [ 0.900581] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). [ 0.900596] [drm] Driver supports precise vblank timestamp query. [ 0.990221] [drm] GMBUS [i915 gmbus panel] timed out, falling back to bit banging on pin 3 [ 1.020888] [drm:i9xx_set_fifo_underrun_reporting] *ERROR* pipe A underrun [ 1.047522] [drm] initialized overlay support [ 1.047637] [drm] Initialized i915 1.6.0 20140905 for 0000:00:02.0 on minor 0 [ 1.100281] [drm] GMBUS [i915 gmbus vga] timed out, falling back to bit banging on pin 2 [ 1.121256] [drm:i9xx_set_fifo_underrun_reporting] *ERROR* pipe A underrun [ 1.200225] [drm] GMBUS [i915 gmbus dpb] timed out, falling back to bit banging on pin 5 [ 1.215081] fbcon: inteldrmfb (fb0) is primary device [ 1.740977] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device [ 1.741047] i915 0000:00:02.0: registered panic notifier [ 26.876525] [drm:i9xx_check_fifo_underruns] *ERROR* pipe B underrun [ 26.904260] [drm:i9xx_set_fifo_underrun_reporting] *ERROR* pipe A underrun [ 56.110048] [drm:i9xx_set_fifo_underrun_reporting] *ERROR* pipe A underrun [ 61.611917] [drm:i9xx_set_fifo_underrun_reporting] *ERROR* pipe A underrun
The VGACNTRL value as saved early on: 0x6104008e That has both VGA_2X_MODE and VGA_PIPE_B_SELECT bits set (plus a whole bunch of bits on the less significant bytes). With patch 69769f9a422bfc62e17399da3590c5e31ac37f24 included VGACNTRL would be set to 0xe104008e. If I mask VGA_2X_MODE I get proper output on my 1440x1050 LVDS display. Thus the following patch on top of 3.18 fixes the issue for me (as an alternative to reverting commit 69769f9a42): diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 9cb5c95..fc4e16d 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -12937,7 +12937,7 @@ static void i915_disable_vga(struct drm_device *dev) * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming * from S3 without preserving (some of?) the other bits. */ - I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE); + I915_WRITE(vga_reg, (dev_priv->bios_vgacntr | VGA_DISP_DISABLE) & + ~VGA_2X_MODE); POSTING_READ(vga_reg); }
Fixed in v3.19-rc4 with commit 01f5a6261cea395f72877aeb7c2fe2d42e1b1e00
(In reply to Bruno from comment #13) > Fixed in v3.19-rc4 with commit 01f5a6261cea395f72877aeb7c2fe2d42e1b1e00 Oh sorry, I failed to close the bug when I committed. Thanks for the report and the follow-up.
Closing resolved+fixed. Verified in v3.19-rc4 by reporter.
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