Created attachment 115286 [details] output System Environment: -------------------------- Platform: SKL Libdrm: (master)libdrm-2.4.60-34-g0d78b37b1cac304ce5e84d1207f0a43abd29c000 Mesa: (master)00bf7d2e9cd60dbd82d25b459c448e11c545a89a Xserver: (master)xorg-server-1.17.0-76-gb1029716e41e252f149b82124a149da180607c96 Xf86_video_intel:(master)2.99.917-282-g83b8528773a0b1e6655fa87c9645a0062cee1359 Libva: (master)062a63932c0f1439aa587aa986bbcfb758ff38f2 Libva_intel_driver:(master)890f538f62707ec07a6accdb65bafcaffc941bb1 Kernel: (drm-intel-nightly)b9fe357740009b89d4bac30b297bfe9808957e6a Bug detailed description: ----------------------------- It fails on SNB+ platforms with mesa master branch. Bisect shows: 07c571a39fa12c3db1c638302de7aed67844609b is the first bad commit. commit 07c571a39fa12c3db1c638302de7aed67844609b Author: Neil Roberts <neil@linux.intel.com> AuthorDate: Fri Apr 10 17:20:21 2015 +0100 Commit: Neil Roberts <neil@linux.intel.com> CommitDate: Tue Apr 14 19:20:28 2015 +0100 i965/skl: Use an exec size of 8 to initialise the message header Commit e93566a15c61c33faa changed the message header code needed to make Skylake use SIMD4x2 so that it uses a register with width 4 instead of 8 as the source register in the send message. However it also changed the width for the dest in the MOV instruction which is used to initialise the header register with the values from g0. The width of the destination is used to determine the exec size in brw_set_dest so this would end up making the MOV have an exec size of 4. I think this would end up leaving the top half of the register uninitialised. The top half of the header has meaningful values so this probably isn't a good idea. This patch just casts the dest register for the MOV instruction back to a vec8 to fix it. It doesn't cause any changes to a Piglit run. Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Reproduce steps: ---------------------------- 1. xinit 2. ./glcts --deqp-case=ES3-CTS.gtf.GL3Tests.uniform_buffer_object.uniform_buffer_object_all_valid_basic_types --deqp-surface-width=64 --deqp-surface-height=64 --deqp-base-seed=1 --deqp-surface-type=window --deqp-gl-config-id=14
Following cases also fail with the same bisect commit: ES3-CTS.gtf.GL3Tests.uniform_buffer_object.uniform_buffer_object_arrays_of_all_valid_basic_types ES3-CTS.gtf.GL3Tests.uniform_buffer_object.uniform_buffer_object_block_member_layouts ES3-CTS.gtf.GL3Tests.uniform_buffer_object.uniform_buffer_object_inherit_and_override_layouts ES3-CTS.gtf.GL3Tests.uniform_buffer_object.uniform_buffer_object_not_whole_uniform_array_active ES3-CTS.gtf.GL3Tests.uniform_buffer_object.uniform_buffer_object_repeat_global_scope_layouts ES3-CTS.gtf.GL3Tests.uniform_buffer_object.uniform_buffer_object_storage_layouts ES3-CTS.gtf.GL3Tests.uniform_buffer_object.uniform_buffer_object_structures_of_all_valid_basic_types ES3-CTS.gtf.GL3Tests.uniform_buffer_object.uniform_buffer_object_unused_uniforms_in_std140 Many ES3-CTS.shaders.uniform_block*(about 570 cases) cases also fail with this commit.
Created attachment 115299 [details] [review] i965/skl: Force the exec size to 8 when initing header for SIMD4x2 Thanks for the bug report. I don't have access to a Skylake machine to test today but I think I have replicated the problem by temporarily forcing this code path on Haswell. Would you be able to test with this patch?
(In reply to Neil Roberts from comment #2) > Created attachment 115299 [details] [review] [review] > i965/skl: Force the exec size to 8 when initing header for SIMD4x2 > > Thanks for the bug report. I don't have access to a Skylake machine to test > today but I think I have replicated the problem by temporarily forcing this > code path on Haswell. > > Would you be able to test with this patch? Test full ogles3conform case, Fixed by this patch.
I've pushed the patch to master: http://cgit.freedesktop.org/mesa/mesa/commit/?id=be119e80c9414aaf5101809c4
Verified.Fixed.
Use of freedesktop.org services, including Bugzilla, is subject to our Code of Conduct. How we collect and use information is described in our Privacy Policy.